Patents by Inventor Gregg A. Bouchard
Gregg A. Bouchard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230111984Abstract: Methods and apparatus for adaptive power profiling in a baseband processing system. In an exemplary embodiment, an apparatus includes one or more processing engines. Each processing engine performs at least one data processing function. The apparatus also includes an adaptive power profile (APP) and a job manager that receives job requests for data processing. The job manager allocates the data processing associated with the job requests to the processing engines based on the adaptive power profile. The adaptive power profile identifies a first group of the processing engines to perform the data processing associated with the job requests, and identifies remaining processing engines to be set to a low power mode.Type: ApplicationFiled: December 5, 2022Publication date: April 13, 2023Applicant: Marvell Asia Pte, Ltd.Inventors: Kalyana S. Venkataraman, Gregg A. Bouchard, Eric Marenger, Ahmed Shahid
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Patent number: 11550384Abstract: Methods and apparatus for adaptive power profiling in a baseband processing system. In an exemplary embodiment, an apparatus includes one or more processing engines. Each processing engine performs at least one data processing function. The apparatus also includes an adaptive power profile (APP) and a job manager that receives job requests for data processing. The job manager allocates the data processing associated with the job requests to the processing engines based on the adaptive power profile. The adaptive power profile identifies a first group of the processing engines to perform the data processing associated with the job requests, and identifies remaining processing engines to be set to a low power mode.Type: GrantFiled: September 24, 2021Date of Patent: January 10, 2023Assignee: Marvell Asia Pte, Ltd.Inventors: Kalyana S Venkataraman, Gregg A Bouchard, Eric Marenger, Ahmed Shahid
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Publication number: 20220011844Abstract: Methods and apparatus for adaptive power profiling in a baseband processing system. In an exemplary embodiment, an apparatus includes one or more processing engines. Each processing engine performs at least one data processing function. The apparatus also includes an adaptive power profile (APP) and a job manager that receives job requests for data processing. The job manager allocates the data processing associated with the job requests to the processing engines based on the adaptive power profile. The adaptive power profile identifies a first group of the processing engines to perform the data processing associated with the job requests, and identifies remaining processing engines to be set to a low power mode.Type: ApplicationFiled: September 24, 2021Publication date: January 13, 2022Applicant: Marvell Asia Pte, Ltd.Inventors: Kalyana Venkataraman, Gregg A. Bouchard, Eric Marenger, Ahmed Shahid
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Patent number: 11132049Abstract: Methods and apparatus for adaptive power profiling in a baseband processing system. In an exemplary embodiment, an apparatus includes one or more processing engines. Each processing engine performs at least one data processing function. The apparatus also includes an adaptive power profile (APP) and a job manager that receives job requests for data processing. The job manager allocates the data processing associated with the job requests to the processing engines based on the adaptive power profile. The adaptive power profile identifies a first group of the processing engines to perform the data processing associated with the job requests, and identifies remaining processing engines to be set to a low power mode.Type: GrantFiled: August 20, 2019Date of Patent: September 28, 2021Assignee: Marvell Asia Pte, Ltd.Inventors: Kalyana S Venkataraman, Gregg A Bouchard, Eric Marenger, Ahmed Shahid
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Publication number: 20190369698Abstract: Methods and apparatus for adaptive power profiling in a baseband processing system. In an exemplary embodiment, an apparatus includes one or more processing engines. Each processing engine performs at least one data processing function. The apparatus also includes an adaptive power profile (APP) and a job manager that receives job requests for data processing. The job manager allocates the data processing associated with the job requests to the processing engines based on the adaptive power profile. The adaptive power profile identifies a first group of the processing engines to perform the data processing associated with the job requests, and identifies remaining processing engines to be set to a low power mode.Type: ApplicationFiled: August 20, 2019Publication date: December 5, 2019Applicant: Cavium, LLCInventors: Kalyana S. Venkataraman, Gregg A. Bouchard, Eric Marenger, Ahmed Shahid
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Patent number: 10496329Abstract: Methods and apparatus for a unified baseband architecture. In an exemplary embodiment, an apparatus includes a shared memory having a plurality of access ports and a scheduler that outputs scheduled jobs. Each scheduled job identifies data processing to be performed. The apparatus also includes a plurality of functional elements coupled to the plurality of access ports, respectively, to access the shared memory. Each functional element is operable to retrieve selected data from the shared memory, process the selected data to generate processed data, and store the processed data into the shared memory based on a received scheduled job.Type: GrantFiled: June 2, 2017Date of Patent: December 3, 2019Assignee: Cavium, LLCInventors: Tejas M. Bhatt, Gregg A. Bouchard, Hong Jik Kim, Jason D. Zebchuk, Ahmed Shahid
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Patent number: 10466964Abstract: An engine architecture for processing finite automata includes a hyper non-deterministic automata (HNA) processor specialized for non-deterministic finite automata (NFA) processing. The HNA processor includes a plurality of super-clusters and an HNA scheduler. Each super-cluster includes a plurality of clusters. Each cluster of the plurality of clusters includes a plurality of HNA processing units (HPUs). A corresponding plurality of HPUs of a corresponding plurality of clusters of at least one selected super-cluster is available as a resource pool of HPUs to the HNA scheduler for assignment of at least one HNA instruction to enable acceleration of a match of at least one regular expression pattern in an input stream received from a network.Type: GrantFiled: September 13, 2017Date of Patent: November 5, 2019Assignee: Cavium, LLCInventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa, Yossef Shanava, Gregg A. Bouchard, Timothy Toshio Nakada
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Patent number: 10423215Abstract: Methods and apparatus for adaptive power profiling in a baseband processing system. In an exemplary embodiment, an apparatus includes one or more processing engines. Each processing engine performs at least one data processing function. The apparatus also includes an adaptive power profile (APP) and a job manager that receives job requests for data processing. The job manager allocates the data processing associated with the job requests to the processing engines based on the adaptive power profile. The adaptive power profile identifies a first group of the processing engines to perform the data processing associated with the job requests, and identifies remaining processing engines to be set to a low power mode.Type: GrantFiled: May 15, 2017Date of Patent: September 24, 2019Assignee: Cavium, LLCInventors: Kalyana S. Venkataraman, Gregg A. Bouchard, Eric Marenger, Ahmed Shahid
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Patent number: 10277510Abstract: In one embodiment, a system includes a data navigation unit configured to navigate through a data structure stored in a first memory to a first representation of at least one rule. The system further includes at least one rule processing unit configured to a) receive the at least one rule based on the first representation of the at least one rule from a second memory to one of the rule processing unit, and b) processing a key using the at least one rule.Type: GrantFiled: August 2, 2012Date of Patent: April 30, 2019Assignee: Cavium, LLCInventors: Rajan Goyal, Gregg A. Bouchard
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Publication number: 20180352557Abstract: Methods and apparatus for a unified baseband architecture. In an exemplary embodiment, an apparatus includes a shared memory having a plurality of access ports and a scheduler that outputs scheduled jobs. Each scheduled job identifies data processing to be performed. The apparatus also includes a plurality of functional elements coupled to the plurality of access ports, respectively, to access the shared memory. Each functional element is operable to retrieve selected data from the shared memory, process the selected data to generate processed data, and store the processed data into the shared memory based on a received scheduled job.Type: ApplicationFiled: June 2, 2017Publication date: December 6, 2018Applicant: Cavium, Inc.Inventors: Tejas M. Bhatt, Gregg A. Bouchard, Hong Jik Kim, Jason D. Zebchuk, Ahmed Shahid
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Publication number: 20180329472Abstract: Methods and apparatus for adaptive power profiling in a baseband processing system. In an exemplary embodiment, an apparatus includes one or more processing engines. Each processing engine performs at least one data processing function. The apparatus also includes an adaptive power profile (APP) and a job manager that receives job requests for data processing. The job manager allocates the data processing associated with the job requests to the processing engines based on the adaptive power profile. The adaptive power profile identifies a first group of the processing engines to perform the data processing associated with the job requests, and identifies remaining processing engines to be set to a low power mode.Type: ApplicationFiled: May 15, 2017Publication date: November 15, 2018Applicant: Cavium, Inc.Inventors: Kalyana S. Venkataraman, Gregg A. Bouchard, Eric Marenger, Ahmed Shahid
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Patent number: 9866540Abstract: In one embodiment, a system includes a format block configured to receive a key, at least one rule, and rule formatting information. The rule can have one or more dimensions. The format block can be further configured to extract each of the dimensions from the at least one rule. The system can further include a plurality of dimension matching engines (DME). Each DME can be configured to receive the key and a corresponding formatted dimension, and process the key and the corresponding dimension for returning a match or nomatch. The system can further include a post processing block configured to analyze the matches or no matches returned from the DMEs and return a response based on the returned matches or nomatches.Type: GrantFiled: May 3, 2016Date of Patent: January 9, 2018Assignee: Cavium, Inc.Inventors: Gregg A. Bouchard, Rajan Goyal, Gregory E. Lund
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Publication number: 20180004483Abstract: An engine architecture for processing finite automata includes a hyper non-deterministic automata (HNA) processor specialized for non-deterministic finite automata (NFA) processing. The HNA processor includes a plurality of super-clusters and an HNA scheduler. Each super-cluster includes a plurality of clusters. Each cluster of the plurality of clusters includes a plurality of HNA processing units (HPUs). A corresponding plurality of HPUs of a corresponding plurality of clusters of at least one selected super-cluster is available as a resource pool of HPUs to the HNA scheduler for assignment of at least one HNA instruction to enable acceleration of a match of at least one regular expression pattern in an input stream received from a network.Type: ApplicationFiled: September 13, 2017Publication date: January 4, 2018Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa, Yossef Shanava, Gregg A. Bouchard, Timothy Toshio Nakada
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Patent number: 9785403Abstract: An engine architecture for processing finite automata includes a hyper non-deterministic automata (HNA) processor specialized for non-deterministic finite automata (NFA) processing. The HNA processor includes a plurality of super-clusters and an HNA scheduler. Each super-cluster includes a plurality of clusters. Each cluster of the plurality of clusters includes a plurality of HNA processing units (HPUs). A corresponding plurality of HPUs of a corresponding plurality of clusters of at least one selected super-cluster is available as a resource pool of HPUs to the HNA scheduler for assignment of at least one HNA instruction to enable acceleration of a match of at least one regular expression pattern in an input stream received from a network.Type: GrantFiled: July 8, 2014Date of Patent: October 10, 2017Assignee: Cavium, Inc.Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa, Yossef Shanava, Gregg A. Bouchard, Timothy Toshio Nakada
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Patent number: 9729527Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.Type: GrantFiled: August 30, 2012Date of Patent: August 8, 2017Assignee: Cavium, Inc.Inventors: Rajan Goyal, Gregg A. Bouchard
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Patent number: 9652505Abstract: An improved content search mechanism uses a graph that includes intelligent nodes avoids the overhead of post processing and improves the overall performance of a content processing application. An intelligent node is similar to a node in a DFA graph but includes a command. The command in the intelligent node allows additional state for the node to be generated and checked. This additional state allows the content search mechanism to traverse the same node with two different interpretations. By generating state for the node, the graph of nodes does not become exponential. It also allows a user function to be called upon reaching a node, which can perform any desired user tasks, including modifying the input data or position.Type: GrantFiled: April 21, 2016Date of Patent: May 16, 2017Assignee: Cavium, Inc.Inventors: Muhammad R. Hussain, David A. Carlson, Gregg A. Bouchard, Trent Parker
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Patent number: 9614762Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. Each of the lookup engines receives a key request associated with a packet and determines a subset of the rules to match against the packet data. A work product may be migrated between lookup engines to complete the rule matching process. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found.Type: GrantFiled: March 31, 2014Date of Patent: April 4, 2017Assignee: Cavium, Inc.Inventors: Rajan Goyal, Gregg A. Bouchard
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Patent number: 9596222Abstract: In one embodiment, a method includes encoding a key matching rule having at least one dimension by storing in a memory (i) a header of the key matching rule that has at least one header field, and (ii) at least one rule value field of the key matching rule corresponding to one of the dimensions.Type: GrantFiled: August 2, 2012Date of Patent: March 14, 2017Assignee: Cavium, Inc.Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa, Gregg A. Bouchard, Gregory E. Lund
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Patent number: 9569366Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.Type: GrantFiled: August 22, 2014Date of Patent: February 14, 2017Assignee: Cavium, Inc.Inventors: Jeffrey A. Pangborn, Gregg A. Bouchard, Rajan Goyal, Richard E. Kessler, Aseem Maheshwari
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Patent number: 9531690Abstract: A method, and corresponding apparatus, of managing processing thread migrations within a plurality of memory clusters, includes embedding, in memory components of the plurality of memory clusters, instructions indicative of processing thread migrations; storing, in one or more memory components of a particular memory cluster among the plurality of memory clusters, data configured to designate the particular memory cluster as a sink memory cluster, the sink memory cluster preventing an incoming migrated processing thread from migrating out of the sink memory cluster; and processing one or more processing threads, in one or more of the plurality of memory clusters, in accordance with at least one of the embedded migration instructions and the data stored in the one or more memory components of the sink memory cluster.Type: GrantFiled: January 8, 2015Date of Patent: December 27, 2016Assignee: Cavium, Inc.Inventors: Najeeb I. Ansari, Gregg A. Bouchard, Rajan Goyal, Jeffrey A. Pangborn, Satyanarayana Lakshmipathi Billa