Abstract: Techniques for combining lookup tables on a programmable integrated circuit are provided. Lookup tables (LUTS) in a design for a programmable circuit can be combined into one mask if they implement the same function. Any two LUTs in a design can be compared to determine if they implement the same function by rearranging the input signals of one of the LUTs with respect to the input terminals of that LUT. Pairs of LUTs can be rejected if they do not share at least N common input signals, or if they have more than M unique input signals.

Abstract: A multiple-pass synthesis technique improves the performance of a design. In a specific embodiment, synthesis is performed in two or more passes. In a first pass, a first synthesis is performed, and in a second or subsequent pass, a second synthesis or resynthesis is performed. During the first synthesis, the logic will be mapped to for example, the logic structures (e.g., logic elements, LUTs, synthesis gates) of the target technology such as a programmable logic device. Alternatively a netlist may be provided from a third party. Before the second synthesis, a fast or abbreviated fit may be performed of the netlist to a specific device (e.g., specific programmable logic device product). Before the second synthesis, the netlist obtained from the first synthesis (or provided by a third party) is unmapped and then the second synthesis is performed. Since a partial fit is performed, the second synthesis has more visibility and optimize the logic better than by using a single synthesis pass.

Abstract: Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.

Abstract: A configuration for a programmable device is determined to implement an incomplete function using at least two logic cells. Function inputs are partitioned into portions associated with first and second logic cells. The partitioning is screened to determine if it is potentially acceptable by determining if a portion of the function can be implemented using a complete look-up table. If the partitioning of the function inputs is potentially acceptable, the function inputs are assigned to the input ports of the logic cells. Variables are assigned to look-up table locations and a correspondence is determined between function input and output values, the variables, and the look-up table locations. Boolean tautology rules are applied to the correspondence to simplify the variables. If the simplified variables are consistent, a configuration is output that includes assignments of function inputs to input ports and look-up table data based on the simplified variables.

Abstract: Disclosed is an LE that can provide a number of advantageous feature. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

Abstract: Methods and code for verifying that modifications or improvements to a synthesizer algorithm do not introduce errors. Specifically, a number or VHDL or Verilog models are chosen. Two netlists are then synthesized from each modeled circuit, once using a unmodified or trusted synthesizer, and once using the modified or improved synthesizer. For each circuit, a set of input test vectors are generated. These vectors are somewhat random in nature, but modified or generated intelligently using knowledge about the circuit to be testing. For each circuit, each netlist is simulated, generating a set of output vectors. These output vectors are compared. If the output vectors match each other for each of the circuits tested, there is a high probability that the improved or modified synthesizer is not introducing new errors into the netlist.