Abstract: A packet-processing method includes looking up a first match-action table on a network interface card (NIC) for a received packet; in response to finding a matching entry indicating an action, queuing the received packet in a first queue and storing the action data in an instruction memory; and responsive to not finding a matching entry, queuing the received packet in the first queue and a second queue. The method includes selecting a first packet from the first queue for processing, which comprises performing a corresponding action stored in the instruction memory; selecting a second packet from the second queue for processing, which comprises forwarding a portion of the second packet to a processor, which looks up a second match-action table; and receiving, from the processor, a lookup result, thereby allowing a third packet in the first queue corresponding to the second packet to be processed based on the lookup result.

Abstract: A packet-processing method includes looking up a first match-action table on a network interface card (NIC) for a received packet; in response to finding a matching entry indicating an action, queuing the received packet in a first queue and storing the action data in an instruction memory; and responsive to not finding a matching entry, queuing the received packet in the first queue and a second queue. The method includes selecting a first packet from the first queue for processing, which comprises performing a corresponding action stored in the instruction memory; selecting a second packet from the second queue for processing, which comprises forwarding a portion of the second packet to a processor, which looks up a second match-action table; and receiving, from the processor, a lookup result, thereby allowing a third packet in the first queue corresponding to the second packet to be processed based on the lookup result.

Abstract: A packet-processing method includes looking up a first match-action table on a network interface card (NIC) for a received packet; in response to finding a matching entry indicating an action, queuing the received packet in a first queue and storing the action data in an instruction memory; and responsive to not finding a matching entry, queuing the received packet in the first queue and a second queue. The method includes selecting a first packet from the first queue for processing, which comprises performing a corresponding action stored in the instruction memory; selecting a second packet from the second queue for processing, which comprises forwarding a portion of the second packet to a processor, which looks up a second match-action table; and receiving, from the processor, a lookup result, thereby allowing a third packet in the first queue corresponding to the second packet to be processed based on the lookup result.

Abstract: A method, system, and apparatus for testing a scalable computer system is provided. In an illustrative implementation, a system for testing a scalable computer system includes configuring a single cell on a partitionable system to create an isolated test channel. A test packet is generated and provided to the test channel. The test channel inserts the test packet into the scalable computer system via a communications link, and a response to the insertion of the test packet is monitored to determine system performance.

Abstract: A crossbar switch having a plurality of ports that allows a debug process to be performed on the switch using one of the plurality of ports to output chip status information. The switch uses a debug block to store chip status information.

Abstract: A method for controlling data transfers through a computer system is provided. First information is transferred to a first node of the computer system regarding availability of a first data storage area within a second node of the computer system for data to be transferred through the second node. Also transferred to the first node is second information regarding availability of a second data storage area within the second node for data to be consumed within the second node. The first information and the second information are then processed to determine if data within the first node destined for the second node is to be transferred to the second node.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to generating processing debug information, processing link identification information, injecting errors across communications links and performing error detection.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to generating processing debug information, processing link identification information, injecting errors across communications links and performing error detection.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to generating processing debug information, processing link identification information, injecting errors across communications links and performing error detection.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: Methods and apparatus in a partitionable computing system. A first link controller is associated with a first partition. A second link controller is associated with a second partition. A computing element communicated with link controllers to establish or deny communication between the partitions.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: A partitionable computer system and method of operating the same is disclosed. The partitionable computer system has a state machine, a processor, and a device controller. The state machine can be configured to monitor the status of a partition of the partitionable computer system. The information provided by the state machine can be used to provide security within the partitionable computing system.