Patents by Inventor Gregg D. Croft

Gregg D. Croft has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8867186
    Abstract: Analog switch circuits, methods for use with analog switch circuits, and devices and systems including analog switch circuits are disclosed herein. Such analog switch circuits include an analog switch input terminal (In), an analog switch output terminal (Out), and an analog switch control terminal (Ctl). During a normal-voltage condition, the input terminal (In) of the analog switch circuit is selectively connected and disconnected to/from the output terminal (Out) in dependence on a control signal received at the control terminal (Ctl). During an over-voltage condition, the input terminal (In) is disconnected from the output terminal (Out) regardless of the control signal received at the control terminal (Ctl). Additionally, during an under-voltage condition, the input terminal (In) is disconnected from the output terminal (Out) regardless of the control signal received at the analog switch control terminal (Ctl).
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: October 21, 2014
    Assignee: Intersil Americas LLC
    Inventor: Gregg D. Croft
  • Publication number: 20140085761
    Abstract: Analog switch circuits, methods for use with analog switch circuits, and devices and systems including analog switch circuits are disclosed herein. Such analog switch circuits include an analog switch input terminal (In), an analog switch output terminal (Out), and an analog switch control terminal (Ctl). During a normal-voltage condition, the input terminal (In) of the analog switch circuit is selectively connected and disconnected to/from the output terminal (Out) in dependence on a control signal received at the control terminal (Ctl). During an over-voltage condition, the input terminal (In) is disconnected from the output terminal (Out) regardless of the control signal received at the control terminal (Ctl). Additionally, during an under-voltage condition, the input terminal (In) is disconnected from the output terminal (Out) regardless of the control signal received at the analog switch control terminal (Ctl).
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: INTERSIL AMERICAS LLC
    Inventor: Gregg D. Croft
  • Publication number: 20110096446
    Abstract: A electrostatic discharge (ESD) clamp for coupling between first and second nodes for providing ESD protection including a clamp circuit and first and second voltage threshold circuits. The clamp circuit limits operating voltage between the first and second nodes to a maximum level when activated. The first and second voltage threshold circuits each have a selectable threshold voltage, such as by coupling one or more voltage threshold devices in series. The first voltage threshold circuit triggers to turn on the clamp circuit when the operating voltage increases above a first voltage threshold. The second voltage threshold circuit triggers when the clamp circuit is turned on and is turned off to turn off the clamp circuit when the operating voltage decreases to the second threshold voltage. The second threshold voltage may be selected at any level above the nominal operating voltage to prevent the clamp from latching.
    Type: Application
    Filed: March 10, 2010
    Publication date: April 28, 2011
    Applicant: INTERSIL AMERICAS INC.
    Inventor: Gregg D. Croft
  • Patent number: 7728649
    Abstract: An integrated analog switch including first and second semiconductor devices and a current mirror. The first device is a switching device having first and second current terminals coupled between first and second switch terminals. When turned off, the body of the first device is pulled to a bias voltage, and a first leakage current flows between its body and the first switch terminal. The second device is a reduced-size replica of the first device having one current terminal coupled to the first switch terminal and having its body pulled to about the bias voltage when turned off. The second device provides a second leakage current which is proportional to the leakage current of the first device. The current mirror circuit mirrors and amplifies the second leakage current to provide a cancellation current which is applied to the first switch terminal to cancel leakage current.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: June 1, 2010
    Assignee: Intersil Americas Inc.
    Inventors: Robert W. Webb, Gregg D. Croft
  • Patent number: 7110933
    Abstract: A method of a modeling metallization parasitics with the use of a simulation program. In one embodiment, a method of simulating interconnect lines in an electronic design automation simulation is disclosed. The method comprises partitioning the interconnect lines into groups of interconnect lines. Each group of interconnect lines does not have interactions with any of the other groups of interconnect lines. Moreover, at least one of the groups of interconnect lines contains at least three interconnect lines. The interconnect lines in each group are modeled. The modeling includes at least one of modeling mutual inductances and modeling of mutual capacitances.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: September 19, 2006
    Assignee: Intersil Americas Inc.
    Inventors: Rex E. Lowther, Gregg D. Croft, Yiqun Lin, Robert Lomenic, James P. Furino, Jr., Joseph A. Czagas
  • Patent number: 6924963
    Abstract: An electrostatic discharge protection circuit for an integrated circuit that reduces unwanted transient currents during normal operations. In one embodiment, the electrostatic discharge protection circuit includes one or more electrostatic bus lines, a plurality of signal bonding pads and charge pumps. The one or more electrostatic bus lines are used to direct electrostatic discharge around internal circuitry. The plurality of signal bonding pads are used to receive external voltage signals. Each signal bonding pad is coupled to an associated electrostatic bus line via an unidirectional conducting device. A charge pump is used on each electrostatic bus line to precharge its associated electrostatic bus line to an associated predetermined voltage level.
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: August 2, 2005
    Assignee: Intersil Americas Inc.
    Inventors: William R. Young, Gregg D. Croft
  • Publication number: 20030151877
    Abstract: An electrostatic discharge protection circuit for an integrated circuit that reduces unwanted transient currents during normal operations. In one embodiment, the electrostatic discharge protection circuit includes one or more electrostatic bus lines, a plurality of signal bonding pads and charge pumps. The one or more electrostatic bus lines are used to direct electrostatic discharge around internal circuitry. The plurality of signal bonding pads are used to receive external voltage signals. Each signal bonding pad is coupled to an associated electrostatic bus line via an unidirectional conducting device. A charge pump is used on each electrostatic bus line to precharge its associated electrostatic bus line to an associated predetermined voltage level.
    Type: Application
    Filed: February 14, 2002
    Publication date: August 14, 2003
    Applicant: INTERSIL AMERICAS INC.
    Inventors: William R. Young, Gregg D. Croft
  • Patent number: 6522117
    Abstract: A reference current/voltage gnereator is insensitive to variations in power supply voltage and temperature. The operational parameters of matched current mirror transistors of the generator are effectively equalized by an auxiliary bias amplifier, whose transistors are matched with and connected to the current mirror transistors of the generator in such a manner as to maintain the same electrical parameters in each of the current mirror legs of the current generator, irrespective of variations in supply voltage. Temperature insensitivity is achieved by making the output current mirror a current that is the sum of two currents whose current paths complementary temperature coefficients.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: February 18, 2003
    Assignee: Intersil Americas Inc.
    Inventors: William R. Young, Gregg D. Croft
  • Publication number: 20030020535
    Abstract: A reference current/voltage gnereator is insensitive to variations in power supply voltage and temperature. The operational parameters of matched current mirror transistors of the generator are effectively equalized by an auxiliary bias amplifier, whose transistors are matched with and connected to the current mirror transistors of the generator in such a manner as to maintain the same electrical parameters in each of the current mirror legs of the current generator, irrespective of variations in supply voltage. Temperature insensitivity is achieved by making the output current mirror a current that is the sum of two currents whose current paths complementary temperature coefficients.
    Type: Application
    Filed: June 13, 2001
    Publication date: January 30, 2003
    Applicant: Intersil Americas Inc.
    Inventors: William R. Young, Gregg D. Croft
  • Patent number: 6064340
    Abstract: An electrostatic discharge locating system may include a plurality of receivers and a central unit. Each receiver may include an antenna. The receivers may receive radio wave signals emanating from an electrostatic discharge event and transmit the signals to the central unit for processing. The central unit may determine the location of an electrostatic discharge event from the relative time of signal reception or the signal amplitudes along with predetermined locations of the receivers.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: May 16, 2000
    Assignee: Intersil Corporation
    Inventors: Gregg D. Croft, Joseph C. Bernier, Rex Lowther
  • Patent number: 5978192
    Abstract: A Schmitt trigger-configured overvoltage protection circuit has a hysteresis turn-on, turn-off characteristic that minimizes its sensitivity to noise, and is effective to protect an integrated circuit against a DC overvoltage condition, and electrostatic discharge-based transients, while allowing `hot` insertion of a device containing the clamping circuit into an already powered-up system. The protection circuit employs a reference device, such as a Zener diode, that enables the clamping circuit trigger threshold to be set at a value that is independent of the power supply voltage.
    Type: Grant
    Filed: November 5, 1997
    Date of Patent: November 2, 1999
    Assignee: Harris Corporation
    Inventors: William R. Young, Gregg D. Croft
  • Patent number: 5708549
    Abstract: An integrated circuit includes protected circuit portions for being electrically connected to an electronic circuit via electrical conductors, and a multiple time constant transient clamping circuit for clamping a transient voltage based upon one of first and second time constants. The first time constant is preferably selected when the integrated circuit is electrically connected to the electronic circuit and is preferably relatively short to permit operation and while protecting the IC from a transient voltage, such as an electrostatic discharge (ESD) event. The longer second time constant is preferably selected when the IC is removed or not electrically connected to the electronic circuit. The longer second time constant is preferably sufficiently long to protect the IC from a transient voltage when the IC is not electrically connected to the circuit board.
    Type: Grant
    Filed: October 4, 1996
    Date of Patent: January 13, 1998
    Assignee: Harris Corporation
    Inventor: Gregg D. Croft
  • Patent number: 5670799
    Abstract: A high voltage protection circuit includes breakdown networks for providing a discharge path between a pair of terminals of a circuit to be protected. Each network conducts current between a supply terminal and another terminal at a low threshold voltage value when power is removed from the supply terminal. The network increases the threshold value when power is applied to the supply terminal to prevent conduction through the breakdown network during normal operation of the circuit to be protected. In one implementation, the protection circuit includes anti-latching circuitry connected to the breakdown network for preventing the breakdown network from latching on after or during the time power is applied to the supply terminals. To minimize the degradation of DC operating characteristics, the leakage currents, due to the protection circuit, between the first terminal and the positive supply terminal, and between the first terminal and the negative supply terminal cancel each other.
    Type: Grant
    Filed: August 26, 1994
    Date of Patent: September 23, 1997
    Assignee: Harris Corporation
    Inventor: Gregg D. Croft
  • Patent number: 5574618
    Abstract: An SCR clamp provides a low impedance discharge path for static charges across on IC's pins. The SCR clamp cathode, cathode, gate anode, and anode gate float when the protected IC is disconnected from its associated circuit elements. Under this condition, the SCR clamp can be turned on at the low Vh and Ih levels of the SCR, allowing the clamp to operate to discharge static electricity at the low voltage determined by SCR junction biases.
    Type: Grant
    Filed: February 17, 1994
    Date of Patent: November 12, 1996
    Assignee: Harris Corporation
    Inventor: Gregg D. Croft
  • Patent number: 5546038
    Abstract: A monolithic voltage clamp provides low impedance, low voltage electrostatic discharge protection for an integrated circuit without affecting the integrated circuit's DC characteristics. First, second, third, and fourth regions of semiconducting material are formed with p-n junctions between each region. A first inductor electrically connects the first and second regions, and a second inductor electrically connects the third and fourth regions. The first and second inductors should each have an inductance which is large enough to delay an increase in bypass current around their respective p-n junctions for a period which is long enough to assure that conduction is sufficient to discharge an electrostatic pulse. In a preferred embodiment, first and second reverse bias diodes are used to electrically connect the invention to one or more input/output nodes.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: August 13, 1996
    Assignee: Harris Corporation
    Inventor: Gregg D. Croft
  • Patent number: 5359211
    Abstract: A high voltage protection circuit includes a breakdown network for providing a discharge path between a pair of terminal of a circuit to be protected. Each network conducts current between a supply terminal and another terminal at a low threshold voltage value when power is removed from the supply terminal. The network increases the threshold value when power is applied to the supply terminal to prevent conduction through the breakdown network during normal operation of the circuit to be protected. In one implementation, the protection circuit includes anti-latching circuitry connected to the breakdown network for preventing the breakdown network from latching on after or during the time power is applied to the supply terminals. To minimize the degradation of DC operating characteristics, the leakage currents, due to the protection circuit, between the first terminal and the positive supply terminal, and between the first terminal and the negative supply terminal cancel each other.
    Type: Grant
    Filed: July 18, 1991
    Date of Patent: October 25, 1994
    Assignee: Harris Corporation
    Inventor: Gregg D. Croft