Abstract: A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.

Abstract: A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.

Abstract: A cache module for a central processing unit has a cache control unit with an interface for a memory, a cache memory coupled with the control unit, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions or data, wherein the address tag bit field is readable and writeable and wherein the cache control unit is operable upon detecting that an address has been written to the address tag bit field to initiate a preload function in which instructions or data from the memory are loaded from the address into the at least one cache line.

Abstract: A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.

Abstract: A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory wherein the cache memory has a plurality of cache lines, each cache line having a storage area for storing instructions to be issued sequentially and associated control bits, wherein at least one cache line of the plurality of cache lines has at least one branch trail control bit which when set provides for an automatic locking function of the cache line in case a predefined branch instruction has been issued.

Abstract: A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions to be issued sequentially and at least one control bit field, wherein the control bit field is coupled with the address tag bit field to mask a predefined number of bits in the address tag bit field.

Abstract: A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.

Abstract: A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions to be issued sequentially and at least one control bit field, wherein the control bit field is coupled with the address tag bit field to mask a predefined number of bits in the address tag bit field.

Abstract: A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory wherein the cache memory has a plurality of cache lines, each cache line having a storage area for storing instructions to be issued sequentially and associated control bits, wherein at least one cache line of the plurality of cache lines has at least one branch trail control bit which when set provides for an automatic locking function of the cache line in case a predefined branch instruction has been issued.

Abstract: A cache module for a central processing unit has a cache control unit with an interface for a memory, a cache memory coupled with the control unit, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions or data, wherein the address tag bit field is readable and writeable and wherein the cache control unit is operable upon detecting that an address has been written to the address tag bit field to initiate a preload function in which instructions or data from the memory are loaded from the address into the at least one cache line.

Abstract: A direct memory access (DMA) controller may comprise a DMA bus, a memory coupled to the DMA bus, a DMA engine coupled with the DMA bus, a cyclic redundancy check (CRC) module coupled with the DMA engine, and a bus interface coupled to the DMA engine and the CRC module.

Abstract: A system for processing a data packet to determine if a replay condition exists for the data packet, wherein the data packet comprises a sequence number for comparison to a highest sequence number. The processing system includes a mask register to store a mask value, wherein the mask value provides an indication of prior receipt by the system of a plurality of data packets, and a shifter comprising an input coupled to receive the mask value from the mask register, wherein the shifter is operable to shift a binary value by a number of bit positions, the number determined by a difference between the sequence number and the highest sequence number.

Abstract: A full-adder post processor performs modulo arithmetic. The full-adder post processor is a hardware implementation able to calculate A mod N, (A+B) mod N and (A?B) mod N. The processor includes a full adder able to add the operands A and B while modulo reduction is accomplished in the processor by successively subtracting the largest possible multiple of the modulus N obtainable by bit shifting prior to subtraction.

Abstract: A system for processing a data packet to determine if a replay condition exists for the data packet, wherein the data packet comprises a sequence number for comparison to a highest sequence number. The processing system includes a mask register to store a mask value, wherein the mask value provides an indication of prior receipt by the system of a plurality of data packets, and a shifter comprising an input coupled to receive the mask value from the mask register, wherein the shifter is operable to shift a binary value by a number of bit positions, the number determined by a difference between the sequence number and the highest sequence number.

Abstract: A full-adder post processor performs modulo arithmetic. The full-adder post processor is a hardware implementation able to calculate A mod N, (A+B) mod N and (A−B) mod N. The processor includes a full adder able to add the operands A and B while modulo reduction is accomplished in the processor by successively subtracting the largest possible multiple of the modulus N obtainable by bit shifting prior to subtraction.

Abstract: The present invention relates to a system and a method for reducing access times for retrieving audio samples. The system uses a wave table cache. The wave table cache allows devices such as a Digital Signal Processor (DSP) to retrieve audio samples in a linear fashion from the wave table cache at a rate much faster than individually fetching the required portions of the audio sample from the main memory of the system. The DSP may then use the audio samples to generate signals to create sounds based on the audio samples.

Abstract: A method for storing and transferring wave table audio samples from system memory to a cache unit. The method creates a linked-list of pages in system memory for storing the audio sample. The linked-list is actually a pointer list indicating the locations in system memory where the audio samples are stored. A Digital Signal Processor (DSP) is able to translate the starting address of the pointer list to retrieve a requested audio sample from the system memory. The requested audio sample is then transferred to the cache unit where the DSP is able to retrieve audio samples in a linear fashion at a rate much faster than individually fetching the required portions of the audio sample from the main memory of the system.

Abstract: A method for storing and transferring wave table audio samples from system memory to a cache unit. The method creates a linked-list of pages in system memory for storing the audio sample. The linked-list is actually a pointer list indicating the locations in system memory where the audio samples are stored. A Digital Signal Processor (DSP) is able to translate the starting address of the pointer list to retrieve a requested audio sample from the system memory. The requested audio sample is then transferred to the cache unit where the DSP is able to retrieve audio samples in a linear fashion at a rate much faster than individually fetching the required portions of the audio sample from the main memory of the system.

Abstract: A multi-mode infrared interface allows for the selection of an encoding mode from a plurality of modes for infrared light transmission. When there is a transmission, an outgoing serial data stream is produced. The infrared interface transmits the serial data stream by infrared light using the selected mode. For example, a first mode is serial data stream transmission where an IR light pulse is transmitted for each bit of data having a first value. A second mode is modulated serial data stream transmission where a modulated IR light pulse is transmitted for each bit of data having a first value. A third mode is REDEYE transmission using the HP Redeye "REDEYE" format. A fourth mode uses a format defined by a user in software.

Abstract: A multi-purpose keyboard controller includes a matrix keyboard control circuit, a serial keyboard control circuit, a PC/AT port control circuit, and an external interface for RTC control. These control circuits are coupled in parallel with the interface logic of the computer system and use the built-in SMI interrupt mechanism of the computer system for reading and writing the keyboard or capturing keypress events. Software BIOS setup is employed to select one of the keyboard control circuits for utilization with the particular personal computer with which the system is employed. The interrupt scheme used by the keyboard interface uses SMI interrupts to the processor and SMI based software routines to read and write the values to and from the keyboard, thereby eliminating the need for dedicating a special hardware interrupt level; so that the system remains compatible with the DOS PC/AT Port 60/64h software interface.