Patents by Inventor GREGG D. WOLFF
GREGG D. WOLFF has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11437116Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.Type: GrantFiled: April 17, 2020Date of Patent: September 6, 2022Assignee: Micron Technology, Inc.Inventors: Christian N. Mohr, Gregg D. Wolff, Christopher G. Wieduwilt, C. Omar Benitez, Dennis G. Montierth
-
Patent number: 11315619Abstract: Apparatuses and methods for distributing row hammer refresh events across a memory device is disclosed. In one embodiment, the present disclosure is directed to an apparatus that includes a first memory configured to receive a sequential series of refresh commands and to replace a first of the sequential refresh commands with a row hammer refresh operation once during a refresh steal cycle, a second memory configured to receive the sequential series of refresh commands at to replace a second of the sequential refresh command with a row hammer refresh operation once during a refresh steal cycle, wherein the first of the sequential refresh commands and the second of the sequential refresh commands are different commands.Type: GrantFiled: November 13, 2019Date of Patent: April 26, 2022Assignee: Micron Technology, Inc.Inventor: Gregg D. Wolff
-
Publication number: 20220100597Abstract: Methods, systems, and apparatuses related to detecting and reporting failures for a memory device are described. When a count of bit-flip errors is above a fail threshold, a memory device can report a failure. Failure reports can indicate a rate at which the memory device is accumulating errors. An offset fail threshold may be applied instead of a default fail threshold, such as a standardized or specified threshold. The offset fail threshold can be a summation of the default fail threshold and an offset determined from an initial error count determined before the memory device has accumulated errors from use.Type: ApplicationFiled: December 10, 2021Publication date: March 31, 2022Inventors: Randall J. Rooney, Gregg D. Wolff
-
Patent number: 11200105Abstract: Methods, systems, and apparatuses related to detecting and reporting failures for a memory device are described. When a count of bit-flip errors is above a fail threshold, a memory device can report a failure. Failure reports can indicate a rate at which the memory device is accumulating errors. An offset fail threshold may be applied instead of a default fail threshold, such as a standardized or specified threshold. The offset fail threshold can be a summation of the default fail threshold and an offset determined from an initial error count determined before the memory device has accumulated errors from use.Type: GrantFiled: December 31, 2018Date of Patent: December 14, 2021Assignee: Micron Technology, Inc.Inventors: Randall J. Rooney, Gregg D. Wolff
-
Publication number: 20200243155Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.Type: ApplicationFiled: April 17, 2020Publication date: July 30, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Christian N. Mohr, Gregg D. Wolff, Christopher G. Wieduwilt, C. Omar Benitez, Dennis G. Montierth
-
Publication number: 20200210267Abstract: Methods, systems, and apparatuses related to detecting and reporting failures for a memory device are described. When a count of bit-flip errors is above a fail threshold, a memory device can report a failure. Failure reports can indicate a rate at which the memory device is accumulating errors. An offset fail threshold may be applied instead of a default fail threshold, such as a standardized or specified threshold. The offset fail threshold can be a summation of the default fail threshold and an offset determined from an initial error count determined before the memory device has accumulated errors from use.Type: ApplicationFiled: December 31, 2018Publication date: July 2, 2020Inventors: Randall J. Rooney, Gregg D. Wolff
-
Patent number: 10643734Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.Type: GrantFiled: June 27, 2018Date of Patent: May 5, 2020Assignee: Micron Technology, Inc.Inventors: Christian N. Mohr, Gregg D. Wolff, Christopher G. Wieduwilt, C. Omar Benitez, Dennis G. Montierth
-
Publication number: 20200082873Abstract: Apparatuses and methods for distributing row hammer refresh events across a memory device is disclosed. In one embodiment, the present disclosure is directed to an apparatus that includes a first memory configured to receive a sequential series of refresh commands and to replace a first of the sequential refresh commands with a row hammer refresh operation once during a refresh steal cycle, a second memory configured to receive the sequential series of refresh commands at to replace a second of the sequential refresh command with a row hammer refresh operation once during a refresh steal cycle, wherein the first of the sequential refresh commands and the second of the sequential refresh commands are different commands.Type: ApplicationFiled: November 13, 2019Publication date: March 12, 2020Applicant: MICRON TECHNOLOGY, INC.Inventor: Gregg D. Wolff
-
Patent number: 10586574Abstract: Cache mode for word lines where the cache mode utilizes an internal timer for a memory cell to disable connection of a voltage to a transistor of a word line driver of the memory cell before an end of a specified end of period. By early disconnection, the local controls of the memory cell may provide additional time to settle after disconnection of the voltage without interfering with operations (e.g., read, write, activate) of the memory cell, since the internal timer may be programmed to be greater than or equal to a worst case scenario for the operations.Type: GrantFiled: May 31, 2019Date of Patent: March 10, 2020Assignee: Micron Technology, Inc.Inventor: Gregg D. Wolff
-
Publication number: 20200005885Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.Type: ApplicationFiled: June 27, 2018Publication date: January 2, 2020Applicant: Micron Technology, Inc.Inventors: Christian N. Mohr, Gregg D. Wolff, Christopher G. Wieduwilt, C. Omar Benitez, Dennis G. Montierth
-
Patent number: 10490251Abstract: Apparatuses and methods for distributing row hammer refresh events across a memory device is disclosed. In one embodiment, the present disclosure is directed to an apparatus that includes a first memory configured to receive a sequential series of refresh commands and to replace a first of the sequential refresh commands with a row hammer refresh operation once during a refresh steal cycle, a second memory configured to receive the sequential series of refresh commands at to replace a second of the sequential refresh command with a row hammer refresh operation once during a refresh steal cycle, wherein the first of the sequential refresh commands and the second of the sequential refresh commands are different commands.Type: GrantFiled: January 30, 2017Date of Patent: November 26, 2019Assignee: Micron Technology, Inc.Inventor: Gregg D. Wolff
-
Publication number: 20190287586Abstract: Cache mode for word lines where the cache mode utilizes an internal timer for a memory cell to disable connection of a voltage to a transistor of a word line driver of the memory cell before an end of a specified end of period. By early disconnection, the local controls of the memory cell may provide additional time to settle after disconnection of the voltage without interfering with operations (e.g., read, write, activate) of the memory cell, since the internal timer may be programmed to be greater than or equal to a worst case scenario for the operations.Type: ApplicationFiled: May 31, 2019Publication date: September 19, 2019Inventor: Gregg D. Wolff
-
Patent number: 10366733Abstract: Cache mode for word lines where the cache mode utilizes an internal timer for a memory cell to disable connection of a voltage to a transistor of a word line driver of the memory cell before an end of a specified end of period. By early disconnection, the local controls of the memory cell may provide additional time to settle after disconnection of the voltage without interfering with operations (e.g., read, write, activate) of the memory cell, since the internal timer may be programmed to be greater than or equal to a worst case scenario for the operations.Type: GrantFiled: March 15, 2018Date of Patent: July 30, 2019Assignee: Micron Technology, Inc.Inventor: Gregg D. Wolff
-
Publication number: 20180218767Abstract: Apparatuses and methods for distributing row hammer refresh events across a memory device is disclosed. In one embodiment, the present disclosure is directed to an apparatus that includes a first memory configured to receive a sequential series of refresh commands and to replace a first of the sequential refresh commands with a row hammer refresh operation once during a refresh steal cycle, a second memory configured to receive the sequential series of refresh commands at to replace a second of the sequential refresh command with a row hammer refresh operation once during a refresh steal cycle, wherein the first of the sequential refresh commands and the second of the sequential refresh commands are different commands.Type: ApplicationFiled: January 30, 2017Publication date: August 2, 2018Applicant: MICRON TECHNOLOGY, INC.Inventor: GREGG D. WOLFF