Abstract: A circuit for freezing a video frame having a first field interlaced with a second field. The circuit generally comprises a memory and a filter. The memory may be configured to present a plurality of coefficient signals that define (i) a first coefficient set for the first field and (ii) a second coefficient set for the second field. The filter may be configured to present a new frame in place of the video frame. The new frame may be generated from either (i) the first field and the first coefficient set in response to freezing on the first field or (ii) the second field and the second coefficient set in response to freezing on the second field.

Abstract: An improved multimedia encoder having features advantageous for use in a computer system. These features provide for the reduction of bandwidth and storage requirements, the enhancement of noise immunity, the evening of computational loading, and the use of multimedia drives for general purpose data storage. In one embodiment, the encoder receives image data representing a sequence of video frames and display text data representing a sequence of text fields to be overlaid on the sequence of video frames. The multimedia encoder produces a compressed video frame only for each subsequent video frame which is different from the current video frame. After each video frame is compressed, it becomes the current frame. The multimedia encoder provides error correction encoding to enhance noise immunity, and performs interframe compression using a dynamic search area to even out computational loading.

Abstract: A recordable DVD disk which includes a read-only sector for specifying a video encoding algorithm to be used for compressing video programs that are to be recorded in the recordable region of the recordable DVD disk. Such disks may be used in a digital video recording system having a programmable video encoder. In one embodiment, the system accepts the recordable DVD disks having a read-only sector for storing customized video encoding algorithms and programs the programmable video encoder with the customized video encoding algorithms prior to encoding and recording a video signal on the disk. By designing the video encoding algorithms to optimize one or more of a number of desirable attributes, the DVD media vendors can then create “classes” of recordable DVD disks, i.e. high capacity, high quality, high speed, high image detail, high color resolution, variable frame rate, etc.

Abstract: A recordable DVD disk which includes a read-only sector for specifying a video encoding algorithm to be used for compressing video programs that are to be recorded in the recordable region of the recordable DVD disk. Such disks may be used in a digital video recording system having a programmable video encoder. In one embodiment, the system accepts the recordable DVD disks having a read-only sector for storing customized video encoding algorithms and programs the programmable video encoder with the customized video encoding algorithms prior to encoding and recording a video signal on the disk. By designing the video encoding algorithms to optimize one or more of a number of desirable attributes, the DVD media vendors can then create “classes” of recordable DVD disks, i.e. high capacity, high quality, high speed, high image detail, high color resolution, variable frame rate, etc.

Abstract: A square estimator computes an estimate of the square of an input number. The input number preferably is provided to combinational logic that logically manipulates the bits of the input number to generate an estimate of the square of the input number. The level of accuracy of the square generator can be programmed or predetermined by including or enabling various term generator logic units. Each term generator logic unit produces an output value that, when added to all of the other output values from the other term generators, provides an estimate of the square of the input number. Additionally, negative correction logic can also be incorporated into the square estimator for producing a negative correction value that when added to the estimate values from the various term generators, permits the square estimator to estimate the square of negative numbers as well as positive numbers.

Abstract: A video filter processes pixel data by storing multiple lines of pixel data in a memory buffer and computes a weighted average of the data using a plurality of multipliers and accumulators. The pixel data which, for example, may represent luminance and/or chrominance values is stored in the buffer in an interleaved fashion. Preferably multiple lines of pixel data is stored in a single buffer, thereby reducing the number of traces that would otherwise be required if a separate buffer was used for each line of pixel data.

Abstract: A programmable audio/video encoder capable of receiving an encoding algorithm from an external digital information source. In one embodiment, the system accepts recordable DVD disks having a read-only sector for storing customized video encoding algorithms and programs the programmable video encoder with the customized video encoding algorithms prior to encoding and recording a video signal on the disk. By designing the video encoding algorithms to optimize one or more of a number of desirable attributes, the DVD media vendors can then create “classes” of recordable DVD disks, i.e. high capacity, high quality, high speed, high image detail, high color resolution, variable frame rate, etc. One programmable video encoder for this embodiment would include an instruction memory for storing the customized video algorithms, a video buffer for buffering the video signal, and a CPU which encodes the video signal according to the customized video algorithms.

Abstract: An audio decoder decodes audio frames included in a Motion Picture Experts Group (MPEG) bitstream for presentation or playing. Each audio frame includes a synchronization code and a frame header, followed by audio data. The synchronization codes are detected, and it is determined that the decoder is synchronized to the bitstream after a first predetermined number, for example three, of successive valid audio frames have been detected. It is similarly determined that the decoder is unsynchronized to the bitstream after a second predetermined number, which can also be three, of successive invalid audio frames have been detected. Each and every frame is determined to be valid if its header parameters are valid, it passes the CRC error check (optional), no syntax errors are detected and its frame length (interval) is as expected.

Abstract: An MPEG audio decoder includes a Vector FIFO buffer and a windowed polyphase filter. Groups of vector samples are zeroed out prior to storage in the Vector FIFO buffer when it is desired to soft-mute an audio output of the decoder.

Abstract: An MPEG audio decoder includes a Vector FIFO buffer and a windowed polyphase filter. Groups of vector samples are zeroed out prior to storage (or after storage, if desired) in the Vector FIFO buffer when error concealment is performed.

Abstract: A Motion Picture Experts Group (MPEG) video/audio data bitstream comprises frames of encoded audio data, each of which includes a plurality of integrally encoded subframes, which are decoded by an audio decoder for presentation. A synchronization unit controls the decoder to skip a subframe if a predetermined decoding time for the subframe is earlier than a current time, and to repeat the subframe if the predetermined decoding time is later than the current time. A typical MPEG audio frame includes 12 subframes, such that skipping or repeating a subframe is 1/12 as noticeable as skipping or repeating an entire frame. A buffer memory stores one or more subframes prior to decoding, such that the subframes can be skipped or repeated by manipulation of a read pointer for the memory.

Abstract: An Inverse Discrete Cosine Transform processor employs symmetry and reusable elements to use a fewer number of gates while maintaining processing speed at an acceptable level. Even and odd sums are generated simultaneously by even and odd sum generators. A butterfly operation is then performed on the on the even and odd sums to produce pairs of transformed elements simultaneously. For an 8.times.8 block, the even and odd sum generators can be designed to a generate four pairs of even and odd sums sequentially. This design allows a single row or column of eight elements to be processed in 4 clock cycles. A horizontal transformation on all eight rows of the block can be performed in 32 cycles. A vertical transformation can then be performed by storing the transformed rows in a second memory, reading out columns from the second memory, and using the same hardware to generate the sums and perform the butterfly operation on the columns.

Abstract: A Video Display FIFO includes a circular buffer and counters that allow the FIFO to properly recover from data alignment problems caused by FIFO underflow. A pair of counters store read and write pointers, which indicate the addresses of data read from and written into the buffer. Another counter stores a count of data in the buffer. Buffer underflow causes the count to go negative and the read pointer to advance ahead of the write pointer. Data written into the buffer while the total count is negative is not read out of the buffer. This allows alignment of the data to be restored.

Abstract: A testing apparatus is integrally formed on a microelectronic integrated circuit chip for testing a plurality of memories including parallel outputs having a total of a first number of bits. The apparatus includes an input unit for writing test data into the memories, a parallel output bus having a second number of bits which is smaller than the first number of bits, and an output unit for selectively connecting outputs of the memories to the output bus such that a total number of bits of the selected outputs is not greater than the second number of bits. The outputs of the memories are connected to the output unit in groups, and the output unit is configured to selectively connect the groups of outputs to the output bus in response to respective control signals to read test data out of the memories. Data is applied from the memories to the output unit in bytes.

Abstract: An audio decoder decodes audio frames included in a Motion Picture Experts Group (MPEG) bitstream for presentation or playing. Each audio frame includes a synchronization code and a frame header, followed by audio data. The synchronization codes are detected, and it is determined that the decoder is synchronized to the bitstream after a first predetermined number, for example three, of successive valid audio frames have been detected. It is similarly determined that the decoder is unsynchronized to the bitstream after a second predetermined number, which can also be three, of successive invalid audio frames have been detected. Each and every frame is determined to be valid if its header parameters are valid, it passes the CRC error check (optional), no syntax errors are detected and its frame length (interval) is as expected.

Abstract: A Motion Picture Experts Group (MPEG) video/audio data bitstream comprises frames of encoded audio data, each of which includes a plurality of integrally encoded subframes, which are decoded by an audio decoder for presentation. A synchronization unit controls the decoder to skip a subframe if a predetermined decoding time for the subframe is earlier than a current time, and to repeat the subframe if the predetermined decoding time is later than the current time. A typical MPEG audio frame includes 12 subframes, such that skipping or repeating a subframe is 1/12 as noticeable as skipping or repeating an entire frame. A buffer memory stores one or more subframes prior to decoding, such that the subframes can be skipped or repeated by manipulation of a read pointer for the memory.

Abstract: A testing apparatus is integrally formed on a microelectronic integrated circuit chip for testing a plurality of memories including parallel outputs having a total of a first number of bits. The apparatus includes an input unit for writing test data into the memories, a parallel output bus having a second number of bits which is smaller than the first number of bits, and an output unit for selectively connecting outputs of the memories to the output bus such that a total number of bits of the selected outputs is not greater than the second number of bits. The outputs of the memories are connected to the output unit in groups, and the output unit is configured to selectively connect the groups of outputs to the output bus in response to respective control signals to read test data out of the memories. Data is applied from the memories to the output unit in bytes.