Abstract: A system for combining write transactions of a large write includes a processor including at least a first die and a second die, and a link coupling the first die and the second die. When a link interface on one die transmits packets to the other die over the link, the link interface identifies, from a queue containing a plurality of write transactions, two or more write transactions in the queue that are candidates for combination based on one or more attributes of each write transaction. The link interface determines whether two or more candidate write transactions are combinable based on a set of conditions. When two or more candidate write transaction are combinable, the link interface combines the candidate write transactions into a single combined write transaction and transmits the combined write transaction.

Abstract: Dynamic network-on-chip traffic throttling, including: determining, by a detector module of a network-on-chip, that a predefined condition is met; sending, by the detector module, a signal to a mediator module of the network-on-chip; and sending, in response to the signal, by the mediator module, an indication to a plurality of agents to implement a traffic throttling policy.

Abstract: An electronic device includes a queue with multiple sub-queues arranged in a logical hierarchy from a lowest sub-queue to a highest sub-queue, each sub-queue including a separate subset of a set of entries of the queue, and a separate age matrix for each sub-queue. The electronic device also includes a controller that stores items in entries in the lowest sub-queue until the lowest sub-queue is full and then stores items in successively next higher sub-queues in the hierarchy. The controller also removes an item that is ready for removal from an entry in the lowest sub-queue. The controller then shifts items in sub-queues in the hierarchy to fill the vacancy in the lowest sub-queue. For the shifting, the controller uses an age matrix associated with each sub-queue to determine an oldest item in that sub-queue and then moves the oldest item to a next lower sub-queue in the hierarchy.

Abstract: A processing system includes a shadow tag memory, which stores a plurality of entries containing coherency information for the cachelines residing at the various levels of private caches. If a cache miss occurs at a private cache, or if coherency information for a cacheline requires updating, a probe is sent to the shadow tag memory maintained at the shared cache to determine whether the requested (or affected) cacheline is stored at another private cache. The probe includes a tag which can be divided into two or more portions. To more efficiently compare the probe tag to the shadow tag entries, the comparison is performed in multiple stages based on the portions of the probe tag.

Abstract: A processing system includes a shadow tag memory, which stores a plurality of entries containing coherency information for the cachelines residing at the various levels of private caches. If a cache miss occurs at a private cache, or if coherency information for a cacheline requires updating, a probe is sent to the shadow tag memory maintained at the shared cache to determine whether the requested (or affected) cacheline is stored at another private cache. The probe includes a tag which can be divided into two or more portions. To more efficiently compare the probe tag to the shadow tag entries, the comparison is performed in multiple stages based on the portions of the probe tag.