Abstract: According to one exemplary embodiment, a memory sensing and latching circuit includes a sensing circuit for evaluating bit lines in a memory array and providing a sensed output. The memory sensing and latching circuit further includes a latching circuit including a dynamic one-shot circuit driven by the sensed output, a sense amplifier enable signal, and a precharge clock. The latching circuit further includes a storage circuit for storing a one-shot output of the dynamic one-shot circuit, where the one-shot output corresponds to the sensed output. The one-shot output of the dynamic one-shot circuit is stored in the storage circuit during an evaluation of the sensed output. The evaluation of the sensed output is responsive to the sense amplifier enable signal.

Abstract: A disclosed embodiment is a circuit for producing a core clock from a system clock so that a core clock cycle is independent of a duty cycle of the system clock. The circuit comprises a system clock receiving sub-circuit for generating a first rising edge of the core clock, a core clock falling edge generation sub-circuit responsive to every rising edge of the core clock, and a self-triggering sub-circuit to trigger a second rising edge of the core clock so as to cause the core clock cycle to be independent of the system clock duty cycle. In one embodiment, the first core clock rising edge may be triggered in response to an initial system clock rising edge. In another embodiment, the first core clock rising edge may be triggered in response to an initial system clock falling edge. The core clock frequency may be twice the frequency of the system clock.

Abstract: According to one exemplary embodiment, a memory sensing and latching circuit includes a sensing circuit for evaluating bit lines in a memory array and providing a sensed output. The memory sensing and latching circuit further includes a latching circuit including a dynamic one-shot circuit driven by the sensed output, a sense amplifier enable signal, and a precharge clock. The latching circuit further includes a storage circuit for storing a one-shot output of the dynamic one-shot circuit, where the one-shot output corresponds to the sensed output. The one-shot output of the dynamic one-shot circuit is stored in the storage circuit during an evaluation of the sensed output. The evaluation of the sensed output is responsive to the sense amplifier enable signal.

Abstract: According to one exemplary embodiment, a memory sensing and latching circuit includes a sensing circuit for evaluating bit lines in a memory array and providing a sensed output. The memory sensing and latching circuit further includes a latching circuit including a dynamic one-shot circuit driven by the sensed output, a sense amplifier enable signal, and a precharge clock. The latching circuit further includes a storage circuit for storing a one-shot output of the dynamic one-shot circuit, where the one-shot output corresponds to the sensed output. The one-shot output of the dynamic one-shot circuit is stored in the storage circuit during an evaluation of the sensed output. The evaluation of the sensed output is responsive to the sense amplifier enable signal.

Abstract: According to one exemplary embodiment, a memory sensing and latching circuit includes a sensing circuit for evaluating bit lines in a memory array and providing a sensed output. The memory sensing and latching circuit further includes a latching circuit including a dynamic one-shot circuit driven by the sensed output, a sense amplifier enable signal, and a precharge clock. The latching circuit further includes a storage circuit for storing a one-shot output of the dynamic one-shot circuit, where the one-shot output corresponds to the sensed output. The one-shot output of the dynamic one-shot circuit is stored in the storage circuit during an evaluation of the sensed output. The evaluation of the sensed output is responsive to the sense amplifier enable signal.

Abstract: A disclosed embodiment is a circuit for producing a core clock from a system clock so that a core clock cycle is independent of a duty cycle of the system clock. The circuit comprises a system clock receiving sub-circuit for generating a first rising edge of the core clock, a core clock falling edge generation sub-circuit responsive to every rising edge of the core clock, and a self-triggering sub-circuit to trigger a second rising edge of the core clock so as to cause the core clock cycle to be independent of the system clock duty cycle. In one embodiment, the first core clock rising edge may be triggered in response to an initial system clock rising edge. In another embodiment, the first core clock rising edge may be triggered in response to an initial system clock falling edge. The core clock frequency may be twice the frequency of the system clock.

Abstract: A control circuit for a FIFO datapath is described. The control circuit consists of a chain of Muller C-elements with adjustable delay elements placed between the output of each Muller C-element and one of the inputs of the preceding and successive Muller C-elements. The adjustable delay elements allow the control circuit to match the delays of processing elements in the datapath, thereby creating overall faster operation.