Patents by Inventor Gregg S Higashi

Gregg S Higashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10797187
    Abstract: Methods and apparatus for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells are provided. A photovoltaic (PV) device generally includes a window layer; an absorber layer disposed below the window layer such that electrons are generated when photons travel through the window layer and are absorbed by the absorber layer; and a plurality of contacts for external connection coupled to the absorber layer, such that all of the contacts for external connection are disposed below the absorber layer and do not block any of the photons from reaching the absorber layer through the window layer. Locating all the contacts on the back side of the PV device avoids solar shadows caused by front side contacts, typically found in conventional solar cells. Therefore, PV devices described herein with back side contacts may allow for increased efficiency when compared to conventional solar cells.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: October 6, 2020
    Assignee: ALTA DEVICES, INC.
    Inventors: Gang He, Isik C. Kizilyalli, Melissa J. Archer, Harry A. Atwater, Thomas J. Gmitter, Andreas G. Hegedus, Gregg S. Higashi
  • Patent number: 9537025
    Abstract: Embodiments generally relate to optoelectronic devices and more specifically, to textured layers in optoelectronic devices. In one embodiment, a method for providing a textured layer in an optoelectronic device includes depositing a first layer of a first material and depositing an island layer of a second material on the first layer. Depositing the island layer includes forming one or more islands of the second material to provide at least one textured surface of the island layer, where the textured surface is operative to cause scattering of light.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: January 3, 2017
    Assignee: ALTA DEVICES, INC.
    Inventors: Brendan M. Kayes, Gregg S. Higashi, Frank Reinhardt, Sylvia Spruytte
  • Publication number: 20160155881
    Abstract: An optoelectronic device with high band-gap absorbers optimized for indoor use and a method of manufacturing are disclosed. The optoelectronic semiconductor device comprises a p-n structure made of one or more compound semiconductors, wherein the p-n structure comprises a base layer and an emitter layer, wherein the base and/or emitter layers comprise materials whose quantum efficiency spectrum is well-matched to a spectrum of incident light, wherein the incident light is from a light source other than the sun; and wherein the device is a flexible single-crystal device. The method for forming an optoelectronic device optimized for the conversion of light from non-solar illumination sources into electricity, comprises depositing a buffer layer on a wafer; depositing a release layer above the buffer layer; depositing a p-n structure above the release layer; and lifting off the p-n structure from the wafer.
    Type: Application
    Filed: January 25, 2016
    Publication date: June 2, 2016
    Inventors: Brendan M. KAYES, Gregg S. HIGASHI, Sam COWLEY, Christopher FRANCE, Ling ZHANG, Gang HE
  • Publication number: 20150243815
    Abstract: Methods and apparatus for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells are provided. A photovoltaic (PV) device generally includes a window layer; an absorber layer disposed below the window layer such that electrons are generated when photons travel through the window layer and are absorbed by the absorber layer; and a plurality of contacts for external connection coupled to the absorber layer, such that all of the contacts for external connection are disposed below the absorber layer and do not block any of the photons from reaching the absorber layer through the window layer. Locating all the contacts on the back side of the PV device avoids solar shadows caused by front side contacts, typically found in conventional solar cells. Therefore, PV devices described herein with back side contacts may allow for increased efficiency when compared to conventional solar cells.
    Type: Application
    Filed: May 7, 2015
    Publication date: August 27, 2015
    Inventors: Gang HE, Isik C. KIZILYALLI, Melissa J. ARCHER, Harry A. ATWATER, Thomas J. GMITTER, Andreas G. HEGEDUS, Gregg S. HIGASHI
  • Publication number: 20090104342
    Abstract: The formation of diagnostic devices on the same substrate used to fabricate a photovoltaic (PV) cell is described. Such devices, also referred to as process diagnostic vehicles (PDVs), are configured for in-line monitoring of electrical characteristics of PV cell features and are formed on the substrate using the same process steps for PV cell fabrication. The data collected via the PDVs can be used to tune or optimize subsequent PV cell fabrication, i.e., used as feedback for the fabrication process. Alternatively, the data collected via PDVs can be fed forward in the fabrication process, so that later process steps performed on a PV cell substrate can be modified to compensate for issues detected on the PV cell substrate via the PDVs.
    Type: Application
    Filed: September 17, 2008
    Publication date: April 23, 2009
    Inventors: Dapeng Wang, Michel R. Frei, Tzay-Fa (Jeff) Su, Vicky Svidenko, Gregg S. Higashi
  • Patent number: 6588437
    Abstract: Apparatus for removal of material in reactions having limited solubility and diffusion. An exemplary system removes unwanted material from the surface of a semiconductor wafer. A flow apparatus is provided for removal of material from a work piece having at least one reaction region containing removable material. The apparatus may include first and second assemblies positionable in spaced-apart relation to form a zone extending between the two assemblies for movement of gaseous material. The first assembly may include a fixture positioned to receive the work piece with the reaction region of the work piece disposed in the zone to allow movement of the gaseous material thereover. A flow assembly is configured to transfer into the zone a gas comprising a condensable material and a reacting species. In another embodiment a system for removal of material from a workpiece includes a chamber, a flow component and a support apparatus.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: July 8, 2003
    Assignee: Agere Systems Inc.
    Inventor: Gregg S Higashi
  • Patent number: 6140187
    Abstract: The present invention provides a process for forming a dopant barrier layer in a gate stack in a semiconductor device. In one advantageous embodiment, the process includes forming a gate oxide on a semiconductor substrate, forming a gate layer on the gate oxide, and forming an ultra thin (less than about 2.5 nm) silicon nitride dopant barrier layer between the gate oxide and the gate layer. The dopant barrier layer provides an excellent barrier to inhibit dopant diffusion through the gate oxide and into the p-channel during the formation of the source/drain areas. Moreover, the formation of this dopant barrier layer and the formation of the gate layer can easily be achieved in a single furnace, if so desired.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: October 31, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Damon K. DeBusk, Gregg S. Higashi, Pradip K. Roy, Nancy Xianghong Zhao
  • Patent number: 5578273
    Abstract: A method and apparatus for cleaning substrates in a process for device fabrication is disclosed. An aqueous solution of hydrogen peroxide and ammonium hydroxide is used to clean the substrates. The concentration of hydrogen peroxide and ammonium hydroxide in the cleaning solution is maintained at a certain level. The life of the cleaning solution is extended by the process. By maintaining the concentrations of the hydrogen peroxide and ammonium hydroxide in the solution within a desired range, the process also provides a cleaning solution that effectively cleans the substates throughout the entire time the solution is used to clean the substrates. The apparatus monitors certain solution parameters such as the pH and the conductivity of the cleaning solution and adds hydrogen peroxide and/or ammonium hydroxide to the cleaning solution to maintain the parameters, and thus the concentration of hydrogen peroxide and ammonium hydroxide, at desired levels.
    Type: Grant
    Filed: August 18, 1995
    Date of Patent: November 26, 1996
    Assignee: Lucent Technologies, Inc.
    Inventors: Karrie J. Hanson, Gregg S. Higashi, Joseph M. Rosamilia
  • Patent number: 5472516
    Abstract: A method and apparatus for cleaning substrates in a process for device fabrication is disclosed. An aqueous solution of hydrogen peroxide and ammonium hydroxide is used to clean the substrates. The concentration of hydrogen peroxide and ammonium hydroxide in the cleaning solution is maintained at a certain level. The life of the cleaning solution is extended by the process. By maintaining the concentrations of the hydrogen peroxide and ammonium hydroxide in the solution within a desired range, the process also provides a cleaning solution that effectively cleans the substates throughout the entire time the solution is used to clean the substrates. The apparatus monitors certain solution parameters such as the pH and the conductivity of the cleaning solution and adds hydrogen peroxide and/or ammonium hydroxide to the cleaning solution to maintain the parameters, and thus the concentration of hydrogen peroxide and ammonium hydroxide, at desired levels.
    Type: Grant
    Filed: April 15, 1994
    Date of Patent: December 5, 1995
    Assignee: AT&T Corp.
    Inventors: Karrie J. Hanson, Gregg S. Higashi, Joseph M. Rosamilia
  • Patent number: 5308796
    Abstract: It has been found that selective metallization in integrated circuits is expeditiously achieved through a copper plating procedure. In this process, palladium silicide is used as a catalytic surface and an electroless plating bath is employed to introduce copper plating only in regions where the silicide is present. Use of this procedure yields superior filling of vias and windows with excellent conductivity.
    Type: Grant
    Filed: April 27, 1993
    Date of Patent: May 3, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Leonard C. Feldman, Gregg S. Higashi, Cecilia Y. Mak, Barry Miller
  • Patent number: 5096840
    Abstract: The inventive method of making a poly-Si emitter transistor (PET) comprises opening an emitter window in a dielectric (typically SiO.sub.2) layer, and depositing onto the thus exposed surface and/or into the single crystal Si material that underlies the exposed surface at least one atomic species. This deposition step is following by the conventional poly-Si deposition, dopant implantation and "drive-in". In a currently preferred embodiment the novel deposition step comprises a low dose, low energy As implantation (5.times.10.sup.13 -2.times.10.sup.15 atoms/cm.sup.2, 0.1-5 keV). The novel method can result in significantly improved device characteristics, e.g., in a doubling of h.sub.FE, as compared to analogous prior art PETs.
    Type: Grant
    Filed: August 15, 1990
    Date of Patent: March 17, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: John C. Bean, Gregg S. Higashi, Bahram Jalali-Farahani, Clifford A. King
  • Patent number: 5091767
    Abstract: Disclosed are strained layer heteroepitaxial structures (e.g., GeSi/Si) that can have low threading dislocation density as well as a substantially planar surface. Furthermore, a large fraction (e.g., >90%) of the total surface are of the structure can be available for device processing. These advantageous features are achieved through utilization of novel "dislocation sinks" on or in the substrate whose height parameter h is less than or about equal to the thickness of the strained heteroepitaxial layer on the substrate. Exemplarily, h.gtoreq.h.sub.c, where h.sub.c is the critical thickness associated with misfit dislocation generation in the substrate/overlayer combination.
    Type: Grant
    Filed: March 18, 1991
    Date of Patent: February 25, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: John C. Bean, Gregg S. Higashi, Robert Hull, Justin L. Peticolas
  • Patent number: 4701347
    Abstract: Patterned metal growth is obtained on a substrate by illuminating the substrate in the presence of a metal containing molecule adsorbed on the substrate. After initial illumination, the photoreacted molecules catalyze further metal growth without further illumination.
    Type: Grant
    Filed: April 18, 1986
    Date of Patent: October 20, 1987
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventor: Gregg S. Higashi