Abstract: A method for clock jitter stress margining of high speed interfaces including generating a jittered clock signal via a clock signal generator of a high speed interface controller card, inputting the jittered clock signal to a control input of a looped-back port of the high speed interface controller card, inputting a test pattern signal to the looped-back port generated from a logic circuitry of the high speed interface controller card, receiving the test pattern signal to the logic circuitry from the looped-back port via the transmitter to the receiver, monitoring a bit error rate of the looped-back port by comparing the received test pattern signal to the inputted test pattern signal, and outputting a fail indication signal if the bit error rate is within a fail threshold.

Abstract: To ensure integrity of non-volatile flash, the controller programs the non-volatile memories with background test patterns and verifies the non-volatile memories during power on self test (POST) operation. In conjunction with verifying the non-volatile memories, the controller may routinely run diagnostics and report status to the storage controller. As part of the storage controller power up routines, the storage controller issues a POST command to the controller via an I2C register that is monitored by the storage controller. The storage controller may determine that the non-volatile flash is functional without any defects, and the controller may remove power from the non-volatile flash to extend its reliability. Periodically, in the background, the controller may run diagnostic routines to detect any failures associated with the volatile memory and the controller itself.

Abstract: A non-volatile flash memory comprises a plurality of non-volatile memories where a first non-volatile memory is pre-programmed (erased) with all ones, and at least a second non-volatile memory is pre-programmed with a seed value that takes advantage of the reduced programming time for less than six zeros. When writing (programming) a data byte, the memory system looks up the data byte in one or more seed tables to determine a portion of non-volatile memory to which the memory system may write the data byte with a reduced programming time. The memory system then records the location of the data byte in an address translation table so the data byte may be accessed.

Abstract: A controller of a memory system is configured to reduce power requirements during memory backup transition. When transitioning to backup mode, the memory system controller performs a number of power saving techniques. The controller may change a number of configuration settings in the volatile memory system, such as reducing output driver strength, increasing differential impedance, increasing on-die termination, disabling receiver input circuitry, and disconnecting the termination voltage network. The controller may also assert a hard reset to the storage controller system to significantly reduce the load and allow the voltage regulator to continue to provide power to the memory system for a longer period of time.

Abstract: A method of a method of replacing bad sectors in a Hard Disk Drive comprises detecting bad sectors on the Hard Disk Drive; remapping the bad sectors to an auxiliary data storage device comprising an Magnetoresistive Random Access Memory connected to the Hard Disk Drive; and storing data on the auxiliary storage device.

Abstract: Because cable length affects signal quality, amplifying signals differently to account for cable length (“tuning”) becomes especially important when high speed signals are used. Cable length information may be stored in a non-volatile memory which may be integrated into a cable assembly or may be a discrete component between the cable and an interface. Rather than using a dedicated data line to the memory component a ground line may be connected to the memory component and multiplexed. During normal operation the selected line is grounded through a switching device. When a cable is detected, a management controller changes the state of the switching device to decouple the selected line from ground to allow the management controller access to the data stored in the memory component, including cable length information. The selected line is then re-coupled to ground and interface circuits may be tuned for the cable length.

Abstract: Systems, methods and computer program products for controlling high-speed network traffic in server blade environments. Exemplary embodiments include a method for controlling high-speed network traffic in a server blade network, the method including identifying a port under test, identifying a debug port, identifying a code state of interest from the port under test and generating a modified IDLE word in response to an identification of a code state of interest from the port under test.

Abstract: A memory system has mechanisms for scavenging capacity of a super capacitor by removing, or reducing, system load from the super capacitor when the super capacitor voltage decays below a low threshold. The mechanisms then restore the system load to the super capacitor when the super capacitor voltage ramps back above a high threshold. A controller may reduce system load by placing a volatile memory system in a standby state and disabling a field effect transistor to remove power from a non-volatile memory system. A controller may adjust the high threshold and/or a low threshold by setting a digitally controlled potentiometer in a threshold detect circuit via an I2C bus.

Abstract: A method for testing a high-speed serial interface, comprising: generating a customized stress test pattern configured to violate an 8bit/10bit-encoding scheme into an expander, the customized stress test pattern is configured to stress the high-speed serial interface beyond marginal limits resulting in less testing to force errors within the high-speed serial interface; transmitting the customized stress test pattern from a transmit port of a first serializer/deserializer device of the high-speed serial interface; and monitoring a receive port of a second serializer/deserializer device to detect errors within the high-speed serial interface.

Abstract: Data storage systems and methods and computer program product for managing data storage systems are provided. The system includes at least first and second storage enclosures, each having a plurality of hard disks configured as first and second arrays of disks and an intra-enclosure path between the first and second arrays. The intra-enclosure path is disabled during normal operation of the storage system. Inter-enclosure paths respectively link the first arrays in the first and second storage enclosures and the second arrays in the first and second storage enclosures and are enabled during normal operation of the storage system.

Abstract: A method, system and computer-usable medium are disclosed for providing management of serial attached small computer system interface (SAS) storage devices. A host computer comprises a storage controller connected to a SAS port expander comprising a plurality of ports that are logically assigned to target storage devices. The device ports of all storage devices physically attached to the SAS port expander are bypassed to remove their logical SAS expander port assignments. The storage controller unbypasses the device ports, allowing it to recognize the presence of all physically attached storage devices. The recognized storage devices are inventoried and storage devices that are not logically assigned a SAS expander port are designated as being spare storage devices. SAS expander ports are logically assigned to the non-spare storage devices and SAS storage operations are performed.

Abstract: In a fibre channel, arbitrated loop (FC-AL) network environment, an operating speed of devices within a switch domain within the network is optimized. The FC-AL switch domain is isolated from an attached storage controller, and a first signal is transmitted to each of a plurality of storage devices within the domain. The first signal comprises a request that each storage device transmit inquiry data to a control and management node (CMN) within the domain. In response to receipt of the inquiry data from each storage device, the speeds at which each storage device is operable are identified and an operational speed is then established for the domain. The established speed may be the fastest speed at which all devices can operate. Alternatively, one or more slower devices may be bypassed and the established speed may be the fastest speed at which all remaining devices can operate.

Abstract: A data storage and retrieval system that comprises a data storage device is disclosed. The data storage and retrieval system further comprises a first LED, a second LED, a third LED, and a fourth LED, interconnected with the data storage device. The data storage device causes the first LED and the second LED to emit first light comprising a first color if the data storage device detects an internal failure. Alternatively, the storage device causes the third LED and the fourth LED to emit second light comprising a second color if the data storage device remains operative.

Abstract: An apparatus is provided and includes a label layer, disposed in a user visible interface of a front bezel, in which an icon is etched, a multi-layer printed circuit board (PCB), abutting a rear surface of the label layer and being configured to form a light source housing that positionally corresponds to that of the icon, a light source assembly, including a substrate, which is fixedly recessed in a rear portion of the light source housing, and a light emitting portion, supported by the substrate, from which light is emitted toward at least the icon, and solder plating to reflect light emitted by the light source away from the preselected icon toward the preselected icon.

Abstract: A method is disclosed to set the signaling rate of a switch domain disposed in an information storage and retrieval system. The method establishes a switch domain target operating speed, and determines if that switch domain target operating speed comprises a first signaling rate. If the switch domain target operating speed comprises a first signaling rate, then the method asserts first Device Control Code bits to each of the plurality of data storage devices, and each of the plurality of data storage devices communicates with the switch using that first signaling rate. If the switch domain target operating speed does not comprise the first signaling rate, then the method asserts second Device Control Code bits to each of the plurality of data storage devices, and each of the plurality of data storage devices communicates with the switch using a second signaling rate.

Abstract: A method to supply power to one or more battery-backup assemblies, wherein the method supplies a first controller, a second controller, a first battery-backup assembly, and a second battery-backup assembly. The method further supplies a power bus interconnected to the first controller, the second controller, the first battery-backup assembly, and the second battery-backup assembly, and a first power supply and a second power supply interconnected with the power bus. The method provides power to the first controller and to the second controller and to the first battery-backup assembly over a first period of time, and provides power to the first controller and to the second controller and to the second battery-backup assembly over a second period of time, where the first period of time differs from the second period of time.

Abstract: A serial SCSI (SAS) storage drive system includes a drive enclosure having a first interface card coupled to one storage controller over a single SAS path and a second interface card coupled to another storage controller over a different single SAS path. At least one disk drive within the enclosure is assigned to the first storage controller and interconnected to the storage controller through the first interface card. At least a second disk drive within the enclosure is assigned to the second storage controller and interconnected to the storage controller through the second interface card. The interface cards are selectively interconnected with each other through a crossover port. In the event of a failure in a storage controller or an interface card, the crossover port may be activated, thereby maintaining access to both sets of disk drives.

Abstract: A storage system includes a RAID adapter, disk array switches, sub-processors, and hard disk drives (HDDs). The system permits the isolation of a suspected faulty HDD to allow diagnostics to be performed without impacting operation of the rest of the system. Upon detection of a possible fault in a target HDD, a private zone is established including the target HDD and one of the sub-processors, thereby isolating the target HDD. The sub-processor performs diagnostic operations, then transmits its results to the adapter. A faulty HDD can then be fully isolated and the private zone is disassembled, allowing the sub-processor to rejoin the network.

Abstract: Components in a data storage subsystem are tracked, and their status monitored, with the use of memory devices such as RFID tags. In the practice of the invention, a component of a data storage subsystem, such as a data recording device, is associated with a memory device, such as but not limited to a Radio Frequency Identification (RFID) tag, that is capable of storing information regarding the data storage component and configured to transmit such information upon interrogation by a reader device. The memory device is coupled to an indicator device that is configured to selectively indicate information about the data storage component.

Abstract: In a RAID storage system, a parity value is generated. The storage system includes a RAID adapter, a plurality of disk array processors managing corresponding sets of RAID storage drives, and a connecting fabric. The RAID adapter initiates a parity generation operation, parallel instructions are dispatched for the array processors to each generate a partial parity value from data blocks on drives on respective managed RAID storage drives, the partial parity value is received in the RAID adapter from each array processor, and the partial parity values are combined in the RAID adapter to generate a complete parity value. The parity value may be an actual parity block to be stored on a hard disk drive or may be a reconstructed data block in the event of a failed drive.