Abstract: A method for implementing a multiplier on a programmable logic device (PLD) is disclosed. Partial product bits of the multiplier are identified and how the partial product bits are to be summed to generate a final product from a multiplier and multiplicand are determined. Chains of PLD cells and cells in the chains of PLD cells for generating and summing the partial product bits are assigned. It is determined whether a bit in an assigned cell in an assigned chain of PLD cells is under-utilized. In response to determining that a bit is under-utilized, the assigning of the chains of PLD cells and cells for generating and summing the partial product bits are changed to improve an overall utilization of the chains of PLD cells and cells in the chains of PLD cells.

Abstract: A method for designing and configuring a system on a field programmable gate array (FPGA) is disclosed. A portion of the system that is implemented greater than a predetermined number of times is identified. A structural netlist that describes how to implement the portion of the system a plurality of times on the FPGA and that leverages a repetitive nature of implementing the portion is generated. The identifying and generating is performed prior to synthesizing and placing other portions of the system that are not implemented greater than the predetermined number of time. Synthesizing, placing, and routing the other portions of the system on the FPGA is performed in accordance with the structural netlist. The FPGA is configured with a configuration file that includes a design for the system that reflects the synthesizing, placing, and routing, wherein the configuring physically transforms resources on the FPGA to implement the system.

Abstract: The present disclosure relates generally to techniques for improving the implementation of certain operations on an integrated circuit. In particular, deep learning techniques, which may use a deep neural network (DNN) topology, may be implemented more efficiently using low-precision weights and activation values by efficiently performing down conversion of data to a lower precision and by preventing data overflow during suitable computations. Further, by more efficiently mapping multipliers to programmable logic on the integrated circuit device, the resources used by the DNN topology to perform, for example, inference tasks may be reduced, resulting in improved integrated circuit operating speeds.

Abstract: A method for designing a system on a target device includes identifying a length for a carry chain that is supported by predefined quanta of a resource on the target device. A plurality of logical adders is mapped onto a single logical adder implemented on the carry chain subject to the identified length to increase logic utilization in a design for the system.

Abstract: The present disclosure relates generally to techniques for enhancing multipliers implemented on an integrated circuit. In particular, by refactoring arithmetic implemented by a multiplier to perform multiplication, routing (e.g., wiring) used by the multiplier may be improved. As a result, the integrated circuit may benefit from increased efficiencies, reduced latency, and reduced resource consumption (e.g., wiring, area, and power) involved with implementing multiplication, which may improve machine learning implementations on the integrated circuit.

Abstract: The present disclosure relates generally to techniques for enhancing packing density of carry-chains implemented on an integrated circuit. In particular, a packed-carry chain may be implemented to redistribute and/or emulate the logic of a first number of arithmetic logic cells of a first and/or second carry-chain using a second number of arithmetic logic cells less than or equal to the first number. By fitting the first and second carry-chain into such a packed carry-chain, the area consumed to perform the arithmetic operations of the first and second carry-chain may be reduced. As a result, the integrated circuit may benefit from increased efficiencies, reduced latency, and reduced resource consumption (e.g., wiring, area, and power).

Abstract: Integrated circuits with digital signal processing (DSP) blocks are provided. A DSP block may include one or more large multiplier circuits. A large multiplier circuit (e.g., an 18×18 or 18×19 multiplier circuit) may be used to support two or more smaller multiplication operations sharing one or two sets of multiplier operands, a complex multiplication, and a sum of two multiplications. If the multiplier products overflow and interfere with one another, correction operations can be performed. Partial products from two or more larger multiplier circuits can be used to combine decomposed partial products. A large multiplier circuit can also be used to support two floating-point mantissa multipliers.

Abstract: Adder trees may be constructed for efficient packing of arithmetic operators into an integrated circuit. The operands of the trees may be truncated to pack an integer number of nodes per logic array block. As a result, arithmetic operations may pack more efficiently onto the integrated circuit while providing increased precision and performance.

Abstract: A method for designing a system on a target device includes identifying an exclusive-OR (XOR) network in a design for the system that matches an XOR network in a library. The XOR network in the design is replaced with a preferred XOR network in the library.

Abstract: A computer-implemented method includes receiving a first circuit design comprising a system of XOR gates, iteratively generating a plurality of candidate physical implementations of the system in adaptive logic modules included in logic array blocks of an integrated circuit, determining an overall metric for each of the plurality of candidate physical implementations using an objective function. The overall metric indicates at least an amount of the system that is implemented by each of the candidate physical implementations in a number of moves. The method also includes implementing an enhanced circuit design including a candidate physical implementation based at least in part on the overall metric of the candidate physical implementation on the integrated circuit.

Abstract: A method of protecting digital words traversing multiple data paths is presented. The method identifies a number of bits for a header of a digital word and determines a number of protection bits for the header. A bit value for each of the protection bits is computed, and the computed bit values of the protection bits are transmitted through one or more data paths.

Abstract: An apparatus includes a transmitter adapted to transmit encoded information to a communication link. The transmitter includes a DC balance skew generator. The DC balance skew generator is adapted to skew a DC balance of the information before information is provided to the communication link.

Abstract: The implementation of serial transmission protocols typically involves the transmission of data in form of serial data streams over multiple serial communication links in parallel. Upon reception, the serial data streams are aggregated to implement a behavior equivalent to the transmission of the data over a single serial communication link. A high-speed serial communication receiver with a central alignment control circuit is provided that performs the identification of word boundaries within each serial data stream, the alignment of all the serial data streams, and the arrangement of the serial communication links in a given order. Using a single central alignment control circuit reduces the circuit area required for performing these operations, facilitates a reduced latency, and can easily control a simplified switching network.

Abstract: Techniques are provided for assisting programmers of electronics components and systems, as well as software components and systems, assess the effectiveness of their designs. Various embodiments provide improved processes for providing statistical feedback to programmers concerning performance features of a system or component they are designing. The techniques provide for faster generation and more effective communication of feedback to the programmer. Such techniques include automatically launching a process for generating such feedback either at periodic intervals or in response to a predefined event. Additionally, techniques are provided for providing the feedback to the programmer in a same working environment in which the programmer is editing the program file, and for displaying the feedback in a format that is more useful to the programmer.

Abstract: The present disclosure provides apparatus and methods for dynamic analog tuning for power reduction. As disclosed herein, the analog controls on a high-speed serial communication channel are dynamically adjusted in a manner so as to either reduce the total system power or move power dissipation between the transmitter and receiver devices, with little or no negative effect to the bit error rate. One embodiment relates to a method for tuning a communication link. The method includes occasionally determining whether the bit error rate for the communication link is acceptably low. Control parameters for analog circuitry of the communication link are adjusted to decrease power used if the bit error rate is acceptably low and are adjusted to increase power used if the bit error rate is not acceptably low. Other embodiments, aspects and features are also disclosed.

Abstract: A first first-in first-out (FIFO) circuit includes a storage circuit, a second first-in first-out (FIFO) circuit, and a third first-in first-out (FIFO) circuit. The storage circuit stores write data at a write address in response to a write clock signal. The storage circuit outputs read data from a read address in response to a read clock signal. A write pointer indicating the write address is synchronized with the write clock signal. A read pointer indicating the read address is synchronized with the read clock signal. The second first-in first-out (FIFO) circuit synchronizes the write pointer with the read clock signal. The third first-in first-out (FIFO) circuit synchronizes the read pointer with the write clock signal.

Abstract: Cyclic redundancy check (CRC) circuitry of a given input data path width is provided to perform CRC on data packets with fixed/variable word length where either the start of packet or the end of packet or both don't need to be aligned with the last and first word or bit of the CRC circuitry's input data path. The CRC circuitry is organized in a hierarchical configuration. A first level performs partial cyclic redundancy checks which are then combined in a second level to perform the cyclic redundancy check from all received data words or bits independent of the start of packet and end of packet positions. The hierarchical configuration enables the increase of the input data path width without incurring the significant increase in area observed for conventional CRC circuitry. This also decreases the number and length of interconnects compared to conventional CRC circuitry, and thus facilitates timing closure.

Abstract: An integrated circuit that includes network interface circuitry is provided. The network interface circuitry may include memory for buffering incoming data and associated control circuitry for loading the incoming data into and retrieving data from memory. The memory may be organized into multiple individually addressable memory blocks. The control circuitry may include read and write barrel shifters, a controller for providing read and write address signals, write address circuitry for controlling the write barrel shifter and for generating write address bits, and read address circuitry for controlling the read barrel shifter and for generating read address bits. The read and write circuitry may each include division and modulus arithmetic circuits for processing the address signals received from the controller and may include control logic for generating the read and write address bits that are used to address each of the multiple memory blocks.

Abstract: An error detection and correction circuit is provided that reduces the number of errors in a data signal sent over a high-speed serial link with little area overhead and without deteriorating the latency of the data transmission. An error detection and correction circuit on the transmit side may compute parity bits for each data packet of N bit-wise interleaved data packets and insert these parity bits into a serial data stream. A transmitter may send the serial data stream with the data packets and the parity bits over a high-speed serial link to a receiver. An error detection and correction circuit on the receive side may locate and correct single-bit errors and detect double-bit errors in each packet of the data signal. Thus, the error correction circuit may correct up to N errors in the N bit-wise interleaved data packets.

Abstract: A method for evaluating structured cells is disclosed. Functions that may be implemented by a candidate structured cell are identified. A cell library having a subset of functions that may be implemented by the structured cell is generated. A system is implemented on a target device using the functions in the cell library. The system on the target device is evaluated.