Patents by Inventor Gregg Williams

Gregg Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12086518
    Abstract: A method for implementing a programmable device is provided. The method may include extracting an underlay from an existing routing network on the programmable device and then mapping a user design to the extracted underlay. The underlay may represent a subset of fast routing wires satisfying predetermined constraints. The underlay may be composed of multiple repeating adjacent logic blocks, each implementing some datapath reduction operation. Implementing circuit designs in this way can dramatically improve circuit performance while cutting down compile times by more than half.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: September 10, 2024
    Assignee: Intel Corporation
    Inventors: Gregg William Baeckler, Martin Langhammer
  • Publication number: 20240290068
    Abstract: A system and a method are for comparing video content with different attributes.
    Type: Application
    Filed: February 24, 2023
    Publication date: August 29, 2024
    Inventors: Gregg William RIEDEL, Hardys Christ EGGUM
  • Publication number: 20240291960
    Abstract: A system and a method are for preparing first content data comprising a first rendition of a media content asset for comparison to second content data comprising a second rendition of the media content asset. The method includes comparing the first content data to the second content data to identify synchronization differences between the first and second content data, where each synchronization difference is indicated by a difference in media content between the first content data for a first time as compared to the second content data for the first time; and when the second content data has already completed a quality control (QC) review, identifying the differences between the first and second content data as synchronization errors in the first content data.
    Type: Application
    Filed: February 24, 2023
    Publication date: August 29, 2024
    Inventors: Gregg William RIEDEL, Hardys Christ EGGUM
  • Publication number: 20240279749
    Abstract: The presently disclosed subject matter relates to methods for rapid, sensitive, and high-throughput nucleic acid testing of biological samples, e.g., blood, serum, or plasma samples from donors, as well as systems capable of performing such high-throughput nucleic acid testing.
    Type: Application
    Filed: April 29, 2022
    Publication date: August 22, 2024
    Applicant: ABBOTT LABORATORIES
    Inventors: Matthew Frankel, Patrick Fritchie, Gregg Williams, Bradley Weston
  • Publication number: 20240239956
    Abstract: The present disclosure relates to a composition that includes a first copolymer having a first repeat unit and a second repeat unit as defined by Structure (I) where is a covalent bond, U1 is a molar fraction of the first repeat unit, (1?U1) is a molar fraction of the second repeat unit, 0?n?20, 0?m?20, 0<U1?1.0, R is a linking group covalently linking the first copolymer to a second copolymer by the covalent bond, and R includes carbon, hydrogen, and sulfur.
    Type: Application
    Filed: December 5, 2023
    Publication date: July 18, 2024
    Inventors: Nicholas A. RORRER, Gregg Tyler BECKHAM, Robin Marcelle CYWAR, Robert David ALLEN, Ryan William CLARKE, Gloria ROSETTO
  • Publication number: 20240210431
    Abstract: Systems and methods for onboard pooling of samples for high-throughput analysis of the samples. Including a sample loading area for receiving a plurality of sample tubes, and a sample transport configured to continually transport individual vessels along a transport path from a sample dispense position to a sample capture and transfer position, with intermediate positions therebetween. At least one pipettor to transfer a first and second samples from the sample loading area to the sample transport and to pool the first sample and the second sample in a vessel on the sample transport to form a pooled sample. A sample transfer mechanism to capture at least a fractionated portion of the pooled sample from the vessel at the sample capture and transfer position and to transfer the at least a fractionated portion of the pooled sample for high-throughput analysis.
    Type: Application
    Filed: April 29, 2022
    Publication date: June 27, 2024
    Applicant: ABBOTT LABORATORIES
    Inventors: Matthew Frankel, Patrick Fritchie, Gregg Williams, Bradley Weston
  • Publication number: 20240214625
    Abstract: An avail comparator and method validates scheduled avail tones. The method includes receiving an automation playlist indicating at least one scheduled avail tone configured to be included in a broadcast. The method includes receiving a feed corresponding to the broadcast. The method includes receiving a signaling for each of the at least one scheduled avail tone based upon the automation playlist. The method includes determining whether the at least one scheduled avail tone was triggered in the broadcast based upon the corresponding signaling.
    Type: Application
    Filed: March 5, 2024
    Publication date: June 27, 2024
    Inventors: Gregg William RIEDEL, Christopher Fulton HUNDERSMARCK, Scott Charles FINDLING, Michael J. McMACKIN
  • Patent number: 12000778
    Abstract: A system and method for encapsulating commercially significant attributes of a hydrocarbon product into a single digital signature are presented. The digital signature may be generated from a physical product sample using optical techniques such as NIR spectroscopy. Digital signatures may be expressed in the form of composition, principle components derived from the spectra, or other properties derived from the original spectra which characterize, and help visualize, the variation present within the signals. Other physical property measurements and contaminant measurements may also be included in the digital signature and may be derived from the same measurement device or separate measurement devices whose output is integrated into a single digital signature. Embodiments of the invention may be used to confirm the identity of a hydrocarbon product, or to verify the composition of a hydrocarbon product.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: June 4, 2024
    Assignee: JP3 Measurement, LLC
    Inventors: Joseph Paul Little, III, Matthew Thomas, Gregg Williams, James Stephen Dixson, III
  • Patent number: 11972015
    Abstract: Removal of PII is provided. Sensor data is captured using sensors of a vehicle. Object detection is performed on the sensor data to create a sematic labeling of objects in the sensor data. A model is utilized to classify regions of the sensor data with a public or private labeling according to the sematic labeling and a PII filter corresponding to a jurisdiction of a current location of the vehicle. The sensor data is utilized in accordance with the public or private labeling.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: April 30, 2024
    Assignee: Ford Global Technologies, LLC
    Inventors: David Michael Herman, Gregg William Byrne, Akshay Vaidya
  • Publication number: 20240020449
    Abstract: Systems or methods of the present disclosure may provide a library including multiple macros that may be pre-compiled prior to implementation of the design. For example, a design may be mapped to one or more macros in the library, and the one or more macros may be placed into and routed between a portion of a region, one region, one or more regions of the integrated circuit device to implement the design. Since the macros may be pre-compiled, compilation time experienced by the designer may correspond to the placement and routing of the one or more macros, which may be less than compilation time for fine-grained operations. The pre-compiled logic within the macros may be set using a lookup table mask to set and/or adjust a functionality of the macro. Additionally or alternatively, the place and route operation may be performed at finer granularities to reduce bottle necks.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 18, 2024
    Inventors: Byron Sinclair, Deshanand P. Singh, Gregg William Baeckler, Mahesh A. Iyer, Michael Kinsner, Chengping Liang, Victor Tzi-on Zhang
  • Publication number: 20240007692
    Abstract: A device, system, and method perform an automatic change over for transport streams. The method is performed at an output server. The method includes selecting a first transport stream. The method includes generating a first portion of an output based on the first transport stream. The method includes selecting a second transport stream. The method includes determining a frametime to synchronize first packets of the first transport stream to second packets of the second transport stream. The frametime is based on a start time of a content item included in the first transport stream and the second transport stream and a completed progression of the content item using the first transport stream. The method includes determining a location in the second transport stream based on the frametime. The method includes generating a second portion of the output based on the second transport stream starting at the location.
    Type: Application
    Filed: September 19, 2023
    Publication date: January 4, 2024
    Inventors: Jeff HESS, Jonathan Edlin CLEGG, Scott DANAHY, Gregg William RIEDEL
  • Patent number: 11812077
    Abstract: A device, system, and method perform an automatic change over for transport streams. The method is performed at an output server. The method includes selecting a first transport stream. The method includes generating a first portion of an output based on the first transport stream. The method includes selecting a second transport stream. The method includes determining a frametime to synchronize first packets of the first transport stream to second packets of the second transport stream. The frametime is based on a start time of a content item included in the first transport stream and the second transport stream and a completed progression of the content item using the first transport stream. The method includes determining a location in the second transport stream based on the frametime. The method includes generating a second portion of the output based on the second transport stream starting at the location.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: November 7, 2023
    Assignee: VIACOM INTERNATIONAL INC.
    Inventors: Jeff Hess, Jonathan Edlin Clegg, Scott Danahy, Gregg William Riedel
  • Patent number: 11712692
    Abstract: A biological sample collection system can include a sample collection vessel having an opening configured to receive a biological sample and a selectively movable valve configured to at least partially associate with the opening of the sample collection vessel. The selectively movable valve can include a post and a valve head associated with a distal portion of the post. The system can additionally include a sealing cap configured to associate with the selectively movable valve and with the sample collection vessel. The sealing cap can include a reagent chamber for storing a measure of sample preservation reagent and associating the sealing cap with the sample collection vessel causes a physical rearrangement of the post and the valve head such that a fluid vent associated with the post aligns with an aperture defined by the valve head allowing fluid communication between the reagent chamber and the sample collection vessel.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: August 1, 2023
    Assignee: Spectrum Solutions L.L.C.
    Inventors: Kevin Gregg Williams, Neil Jeremy Johnson
  • Publication number: 20230239136
    Abstract: Integrated circuits, methods, and circuitry are provided for performing multiplication such as that used in Galois field counter mode (GCM) hash computations. An integrated circuit may include selection circuitry to provide one of several powers of a hash key. A Galois field multiplier may receive the one of the powers of the hash key and a hash sequence and generate one or more values. The Galois field multiplier may include multiple levels of pipeline stages. An adder may receive the one or more values and provide a summation of the one or more values in computing a GCM hash.
    Type: Application
    Filed: March 31, 2023
    Publication date: July 27, 2023
    Inventors: Sergey Vladimirovich Gribok, Gregg William Baeckler, Bogdan Pasca, Martin Langhammer
  • Publication number: 20230198526
    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.
    Type: Application
    Filed: February 16, 2023
    Publication date: June 22, 2023
    Inventors: Dheeraj Subbareddy, MD Altaf Hossain, Ankireddy Nalamalpu, Robert Sankman, Ravindranath Mahajan, Gregg William Baeckler
  • Publication number: 20230107160
    Abstract: A device, system, and method perform an automatic change over for transport streams. The method is performed at an output server. The method includes selecting a first transport stream. The method includes generating a first portion of an output based on the first transport stream. The method includes selecting a second transport stream. The method includes determining a frametime to synchronize first packets of the first transport stream to second packets of the second transport stream. The frametime is based on a start time of a content item included in the first transport stream and the second transport stream and a completed progression of the content item using the first transport stream. The method includes determining a location in the second transport stream based on the frametime. The method includes generating a second portion of the output based on the second transport stream starting at the location.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 6, 2023
    Inventors: Jeff HESS, Jonathan Edlin CLEGG, Scott DANAHY, Gregg William RIEDEL
  • Patent number: 11595045
    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: February 28, 2023
    Assignee: Intel Corporation
    Inventors: Dheeraj Subbareddy, MD Altaf Hossain, Ankireddy Nalamalpu, Robert Sankman, Ravindranath Mahajan, Gregg William Baeckler
  • Publication number: 20230054207
    Abstract: A biological sample collection system includes: a sample collection vessel having a sample collection chamber for receiving a biological sample; a sealing cap including a reagent chamber for storing a sample preservation reagent and being configured to associate with the sample collection vessel; and a selectively movable valve at least partially disposed within the sealing cap. The selectively movable valve includes a post with an interior chamber and fluid vent and a valve head associated with a distal portion of the post that initially occludes the fluid vent when the valve is in the closed configuration. Associating the sealing cap with the sample collection vessel causes a physical rearrangement of the post and the valve head in order for the fluid vent to become unoccluded by the valve head, thereby placing the valve in an open configuration and allowing fluid communication between the reagent chamber and the sample collection vessel.
    Type: Application
    Filed: November 4, 2022
    Publication date: February 23, 2023
    Inventors: Kevin Gregg WILLIAMS, Neil Jeremy JOHNSON
  • Publication number: 20230027064
    Abstract: Systems and methods of the present disclosure provide techniques for reducing power consumption of a large combinational circuit using register insertion. In particular, a large circuit may be analyzed to determine the amount of signal switching at various logical points (e.g., stages in the computation) of the circuit. A clock sequence with many pulses in the period of a clock that runs the large combinatorial circuit may be generated. To balance the amount of signal switching at various logical points in the circuit, registers may be inserted at certain points in the large circuit with the clock pulses of the clock sequence assigned to the registers that may not have a constant frequency or may be phase shifted versions of the main clock.
    Type: Application
    Filed: September 30, 2022
    Publication date: January 26, 2023
    Inventors: Martin Langhammer, Gregg William Baeckler, Sergey Vladimirovich Gribok, Mahesh A. Iyer
  • Publication number: 20230018414
    Abstract: The present disclosure describes techniques for incorporating pipelined DSP blocks or other types of embedded functions into a logic circuit with a slower clock rate without any clock crossing complexities, and at the same time managing the power consumption of the more complex design that results from it. The techniques include generating a faster clock or several faster clocks that may have a faster clock rate than the clock used by the logic circuit and that may be used as clock input to the embedded pipelined DSP blocks. In addition, the present disclosure describes techniques for generating, improving, and using the faster clock to sample the output of a logic circuit using pulses of generated faster clock, which may allow to increase the clock frequency of the circuit to an optimal level, while maintaining functional correctness.
    Type: Application
    Filed: September 29, 2022
    Publication date: January 19, 2023
    Inventors: Martin Langhammer, Gregg William Baeckler, Sergey Vladimirovich Gribok, Mahesh A. Iyer