Patents by Inventor Gregor BRACHER

Gregor BRACHER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11024712
    Abstract: A semiconductor device is proposed. The semiconductor device includes a source region of a field effect transistor having a first conductivity type, a body region of the field effect transistor having a second conductivity type, and a drain region of the field effect transistor having the first conductivity type. The source region, the drain region, and the body region are located in a semiconductor substrate of the semiconductor device and the body region is located between the source region and the drain region. The drain region extends from the body region through a buried portion of the drain region to a drain contact portion of the drain region located at a surface of the semiconductor substrate, the buried portion of the drain region is located beneath a spacer doping region, and the spacer doping region is located within the semiconductor substrate.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 1, 2021
    Assignee: Intel IP Corporation
    Inventors: Vase Jovanov, Peter Baumgartner, Gregor Bracher, Luis Giles, Uwe Hodel, Andreas Lachmann, Philipp Riess, Karl-Henrik Ryden
  • Publication number: 20200006483
    Abstract: A semiconductor device is proposed. The semiconductor device includes a source region of a field effect transistor having a first conductivity type, a body region of the field effect transistor having a second conductivity type, and a drain region of the field effect transistor having the first conductivity type. The source region, the drain region, and the body region are located in a semiconductor substrate of the semiconductor device and the body region is located between the source region and the drain region. The drain region extends from the body region through a buried portion of the drain region to a drain contact portion of the drain region located at a surface of the semiconductor substrate, the buried portion of the drain region is located beneath a spacer doping region, and the spacer doping region is located within the semiconductor substrate.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Vase JOVANOV, Peter BAUMGARTNER, Gregor BRACHER, Luis GILES, Uwe HODEL, Andreas LACHMANN, Philipp RIESS, Karl-Henrik RYDEN