Abstract: An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).

Abstract: Uniformity of a sputtered conductive barrier layer (50) or seed layer (52) across a semiconductor substrate (18, 42) is improved by incorporating a plurality of electromagnets (26) in or around the sputtering chamber (14) which can be independently powered. In other words, each individual electromagnet can be turned on or off, and/or the amount of power being supplied to each electromagnet (and thus the magnetic field generated by each electromagnet) can be varied independently. Further, the sputtering system (10) includes connection to a computer (30) that is either integral to or connected to a metrology tool (28). The metrology tool measures uniformity of a layer deposited by the sputtering system, analyzes the measurements and feeds back information to the sputtering system as to how to vary the power being supplied to the plurality of electromagnets to improve layer uniformity.

Abstract: Uniformity of a sputtered conductive barrier layer (50) or seed layer (52) across a semiconductor substrate (18, 42) is improved by incorporating a plurality of electromagnets (26) in or around the sputtering chamber (14) which can be independently powered. In other words, each individual electromagnet can be turned on or off, and/or the amount of power being supplied to each electromagnet (and thus the magnetic field generated by each electromagnet) can be varied independently. Further, the sputtering system (10) includes connection to a computer (30) that is either integral to or connected to a metrology tool (28). The metrology tool measures uniformity of a layer deposited by the sputtering system, analyzes the measurements and feeds back information to the sputtering system as to how to vary the power being supplied to the plurality of electromagnets to improve layer uniformity.

Abstract: An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).

Abstract: An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).

Abstract: An interconnect (60) is formed overlying a substrate (10). In one embodiment, an adhesion/barrier layer (81), a copper-alloy seed layer (42), and a copper film (43) are deposited overlying the substrate (10), and the substrate (10) is annealed. In an alternate embodiment, a copper film is deposited over the substrate, and the copper film is annealed. In yet another embodiment, an adhesion/barrier layer (81), a seed layer (82), a conductive film (83), and a copper-alloy capping film (84) are deposited over the substrate (10) to form an interconnect (92). The deposition and annealing steps can be performed on a common processing platform.