Patents by Inventor Gregor Braeckelmann

Gregor Braeckelmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6713381
    Abstract: An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: March 30, 2004
    Assignee: Motorola, Inc.
    Inventors: Alexander L. Barr, Suresh Venkatesan, David B. Clegg, Rebecca G. Cole, Olubunmi Adetutu, Stuart E. Greer, Brian G. Anthony, Ramnath Venkatraman, Gregor Braeckelmann, Douglas M. Reber, Stephen R. Crown
  • Publication number: 20020093098
    Abstract: An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).
    Type: Application
    Filed: January 18, 2002
    Publication date: July 18, 2002
    Inventors: Alexander L. Barr, Suresh Venkatesan, David B. Clegg, Rebecca G. Cole, Olubunmi Adetutu, Stuart E. Greer, Brian G. Anthony, Ramnath Venkatraman, Gregor Braeckelmann, Douglas M. Reber, Stephen R. Crown
  • Publication number: 20020000665
    Abstract: An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).
    Type: Application
    Filed: April 5, 1999
    Publication date: January 3, 2002
    Inventors: ALEXANDER L. BARR, SURESH VENKATESAN, DAVID B. CLEGG, REBECCA G. COLE, OLUBUNMI ADETUTU, STUART E. GREER, BRIAN G. ANTHONY, RAMNATH VENKATRAMAN, GREGOR BRAECKELMANN, DOUGLAS M. REBER, STEPHEN R. CROWN
  • Patent number: 6218302
    Abstract: An interconnect (60) is formed overlying a substrate (10). In one embodiment, an adhesion/barrier layer (81), a copper-alloy seed layer (42), and a copper film (43) are deposited overlying the substrate (10), and the substrate (10) is annealed. In an alternate embodiment, a copper film is deposited over the substrate, and the copper film is annealed. In yet another embodiment, an adhesion/barrier layer (81), a seed layer (82), a conductive film (83), and a copper-alloy capping film (84) are deposited over the substrate (10) to form an interconnect (92). The deposition and annealing steps can be performed on a common processing platform.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: April 17, 2001
    Assignee: Motorola Inc.
    Inventors: Gregor Braeckelmann, Ramnath Venkatraman, Matthew Thomas Herrick, Cindy R. Simpson, Robert W. Fiordalice, Dean J. Denning, Ajay Jain, Cristiano Capasso