Patents by Inventor Gregor Langer
Gregor Langer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096842Abstract: A method for fabricating a SiC power semiconductor device includes: providing a SiC power semiconductor die; depositing a metallization layer over the power semiconductor die, the metallization layer including a first metal; arranging the power semiconductor die over a die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and diffusion soldering the power semiconductor die to the die carrier such that a first intermetallic compound is formed between the power semiconductor die and the plating, the first intermetallic compound including Ni3Sn4.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Ralf Otremba, Gregor Langer, Paul Frank, Alexander Heinrich, Alexandra Ludsteck-Pechloff, Daniel Pedone
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Publication number: 20240055256Abstract: The disclosure relates to a method for manufacturing a contact on a silicon carbide semiconductor substrate and to a silicon carbide semiconductor device comprising a crystalline silicon carbide semiconductor substrate and a contact layer directly in contact with the silicon carbide semiconductor substrate surface and having, at an interface to the semiconductor substrate, a contact phase portion comprising at least a metal, silicon, and carbon. The method comprises the acts of providing a crystalline silicon carbide semiconductor substrate, depositing a metallic contact material layer onto the crystalline silicon carbide semiconductor substrate, and irradiating at least a part of the silicon carbide semiconductor substrate and at least a part of the metallic contact material layer at their interface with at least one thermal annealing laser beam, thereby generating a contact phase portion at the interface, wherein the contact phase portion comprises at least a metal, silicon, and carbon.Type: ApplicationFiled: August 7, 2023Publication date: February 15, 2024Inventors: Ravi Keshav JOSHI, Kristijan Luka MLETSCHNIG, Axel KÖNIG, Gregor LANGER
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Publication number: 20240006218Abstract: A method of manufacturing a semiconductor device in a semiconductor body is proposed. The method includes processing a semiconductor body at a first surface of the semiconductor body. The method further includes attaching the semiconductor body to a carrier via the first surface. The carrier includes an inner part and an outer part at least partly surrounding the inner part. The method further includes processing the semiconductor body at a second surface opposite to the first surface. The method further includes detaching the inner part of the carrier from the semiconductor body.Type: ApplicationFiled: June 20, 2023Publication date: January 4, 2024Inventors: Gregor Langer, Bernhard Goller, Nilesha Mishra, Matteo Piccin, Franz-Josef Pichler
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Publication number: 20230420257Abstract: A chip is provided. In an embodiment, the chip includes a silicon carbide substrate, a first sputtered metal layer on the silicon carbide substrate, and at least one second sputtered metal layer on the first sputtered metal layer. The first sputtered metal layer and the at least one second sputtered metal layer form an electrical contact. In another embodiment, the chip includes a silicon carbide substrate, a nickel-silicon layer on the silicon carbide substrate, and a layer sequence including a titanium layer, a nickel-containing layer, and a gold-tin or silver layer on the nickel-silicon layer.Type: ApplicationFiled: August 31, 2023Publication date: December 28, 2023Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
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Patent number: 11798807Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.Type: GrantFiled: May 10, 2021Date of Patent: October 24, 2023Assignee: Infineon Technologies AGInventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
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Publication number: 20230317666Abstract: A semiconductor device and a method of manufacturing a semiconductor are provided. In an embodiment, a method of manufacturing a semiconductor device is provided. A first layer is formed over a silicon carbide (SiC) layer. The first layer has a first surface distal the SiC layer and a second surface proximal the SiC layer. The first layer includes a metal. First thermal energy may be directed to the first surface of the first layer to form a metal silicide layer from the metal of the first layer and silicon of the SiC layer. The metal silicide layer has a first surface distal the SiC layer and a second surface proximal the SiC layer.Type: ApplicationFiled: April 4, 2022Publication date: October 5, 2023Inventors: Gregor Langer, Michael Roesner, Ewald Wiltsche, Ronny Kern, Victorina Poenariu, Axel Koenig
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Publication number: 20230215729Abstract: A method of manufacturing a metal silicide layer comprises performing laser thermal annealing of a surface region of a silicon carbide (SiC) substrate, exposing a surface of a thus obtained silicon layer, depositing a metal layer above the exposed silicon layer, and/or thermally treating a stack of layers, comprising the silicon layer and the metal layer, to form a metal silicide layer. Alternatively and/or additionally, the method may comprise depositing a silicon layer above a SiC substrate, depositing a metal layer, and/or performing laser thermal annealing of the SiC substrate and a stack of layers above the SiC substrate to form a metal silicide layer, wherein the stack of layers comprises the silicon layer and the metal layer. Moreover, a semiconductor device is described, comprising a SiC substrate, a metal silicide layer, and a polycrystalline layer in direct contact with the SiC substrate and the metal silicide layer.Type: ApplicationFiled: December 29, 2022Publication date: July 6, 2023Inventors: Hans-Joachim SCHULZE, Florian Markus GRASSE, Moriz JELINEK, Axel KÖNIG, Gregor LANGER, Bemhard LEITL, Kristijan Luka MLETSCHNIG, Werner SCHUSTEREDER
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Publication number: 20210265168Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
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Publication number: 20210225795Abstract: A SiC power semiconductor device includes: a power semiconductor die including SiC and a metallization layer, wherein the metallization layer includes a first metal; a die carrier, wherein the power semiconductor die is arranged over the die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and a first intermetallic compound arranged between the power semiconductor die and the plating and including Ni3Sn4.Type: ApplicationFiled: January 15, 2021Publication date: July 22, 2021Inventors: Ralf Otremba, Gregor Langer, Paul Frank, Alexander Heinrich, Alexandra Ludsteck-Pechloff, Daniel Pedone
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Patent number: 11043383Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a chemical cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.Type: GrantFiled: May 24, 2019Date of Patent: June 22, 2021Assignee: Infineon Technologies AGInventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
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Publication number: 20200323081Abstract: A method for embedding a component in a printed circuit board or a printed circuit board intermediate product, wherein the printed circuit board or the printed circuit board intermediate product comprises at least one insulating layer made of a prepreg material, and the component is fixed by the resin of the prepreg material, is characterized by the following steps: providing a combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, wherein this combination includes at least one curable prepreg material; creating a clearance in the combination for accommodating the component to be embedded; covering at least the region of the clearance with a first temporary carrier layer on a first side of the combination; positioning the component to be embedded in the clearance by way of the first temporary carrier layer; covering at least the region of the clearance on the second side of the combination with a second temporary carrier layer; compressing the combinatioType: ApplicationFiled: June 22, 2020Publication date: October 8, 2020Applicant: AT&S Austria Technologie & Systemtechnik AktiengesellschaftInventors: Timo Schwarz, Andreas Zluc, Gregor Langer, Johannes Stahr
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Patent number: 10779413Abstract: A method for embedding a component in a printed circuit board or a printed circuit board intermediate product, wherein the printed circuit board or the printed circuit board intermediate product comprises at least one insulating layer made of a prepreg material, and the component is fixed by the resin of the prepreg material, is characterized by the following steps: providing a combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, wherein this combination includes at least one curable prepreg material; creating a clearance in the combination for accommodating the component to be embedded; covering at least the region of the clearance with a first temporary carrier layer on a first side of the combination; positioning the component to be embedded in the clearance by way of the first temporary carrier layer; covering at least the region of the clearance on the second side of the combination with a second temporary carrier layer; compressing the combinatioType: GrantFiled: December 12, 2014Date of Patent: September 15, 2020Assignee: AT&S Austria Technologie & Systemtechnik AktiengesellschaftInventors: Timo Schwarz, Andreas Zluc, Gregor Langer, Johannes Stahr
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Publication number: 20190362973Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a chemical cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.Type: ApplicationFiled: May 24, 2019Publication date: November 28, 2019Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
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Publication number: 20190221718Abstract: An electronic module and method for the production of the electronic module in accordance with some embodiments of the invention are disclosed. The electronic module includes at least one electronic component affixed to a conductive layer by means of sticky electrically insulating layer, where the electronic component is embedded in a transparent foil. The electronic module is produces by providing an electrically conductive layer. At least one electronic component is affixed to the electrically conductive layer by means of a sticky electrically insulating layer and embedded in a transparent foil. The at least one electronic component is electronically contacted with the conductive layer.Type: ApplicationFiled: March 27, 2019Publication date: July 18, 2019Applicant: AT&S Austria Technologie & Systemtechnik AktiengesellschaftInventors: Gregor Langer, Johannes Stahr
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Patent number: 10283680Abstract: An electronic module and method for the production of the electronic module in accordance with some embodiments of the invention are disclosed. The electronic module includes at least one electronic component affixed to a conductive layer by means of sticky electrically insulating layer, where the electronic component is embedded in a transparent foil. The electronic module is produces by providing an electrically conductive layer. At least one electronic component is affixed to the electrically conductive layer by means of a sticky electrically insulating layer and embedded in a transparent foil. The at least one electronic component is electronically contacted with the conductive layer.Type: GrantFiled: May 5, 2016Date of Patent: May 7, 2019Assignee: AT&S Austria Technologie & Systemtechnik AktiengesellschaftInventors: Gregor Langer, Johannes Stahr
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Patent number: 9903539Abstract: The invention relates to a circuit board element (1) comprising a substrate (2), on which at least one dielectric layer (7) is arranged, and at least one LED (light-emitting diode) (10), wherein at least one channel-shaped waveguide cavity (11) leading away from the LED (10) is provided in the dielectric layer (7), which waveguide cavity leads to at least one integrated light-sensitive component (12), preferably a photo-diode or photocell, arranged for examining the light emission, wherein the LED (10) is preferably also arranged in a cavity (9) that is connected to the waveguide cavity (11). The invention further relates to a method for producing such a circuit board element (1).Type: GrantFiled: March 20, 2012Date of Patent: February 27, 2018Assignee: AT & S AUSTRIA TECHNOLOGIE & SYSTEMTECHNIK AKTIENGESELLSCHAFTInventors: Alexander Kasper, Gregor Langer
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Patent number: 9713248Abstract: Method for the manufacture of a printed circuit board with at least one cavity for the accommodation of an electronic component, wherein the cavity walls exhibit a reflective, in particular mirrored reflector layer characterized by the following steps: Provision of a printed circuit board, Application of a temporary protective layer onto at least a section of the surface of the circuit board, Creation of the cavity by way of penetration of the protective layer in the region of the cavity, Application of the reflector layer, Removal of the temporary protective layer.Type: GrantFiled: January 21, 2015Date of Patent: July 18, 2017Assignee: AT&S Austria Technologie & Systemtechnik AktiengesellschaftInventors: Gregor Langer, Mario Damej, Ferdinand Lutschounig
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Publication number: 20160353566Abstract: Method for the manufacture of a printed circuit board with at least one cavity for the accommodation of an electronic component, wherein the cavity walls exhibit a reflective, in particular mirrored reflector layer characterized by the following steps: Provision of a printed circuit board, Application of a temporary protective layer onto at least a section of the surface of the circuit board, Creation of the cavity by way of penetration of the protective layer in the region of the cavity, Application of the reflector layer, Removal of the temporary protective layer.Type: ApplicationFiled: January 21, 2015Publication date: December 1, 2016Applicant: AT&S Austria Technologie & Systemtechnik AktiengesellschaftInventors: Gregor LANGER, Mario DAMEJ, Ferdinand LUTSCHOUNIG
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Publication number: 20160329469Abstract: An electronic module and method for the production of the electronic module in accordance with some embodiments of the invention are disclosed. The electronic module includes at least one electronic component affixed to a conductive layer by means of sticky electrically insulating layer, where the electronic component is embedded in a transparent foil. The electronic module is produces by providing an electrically conductive layer. At least one electronic component is affixed to the electrically conductive layer by means of a sticky electrically insulating layer and embedded in a transparent foil. The at least one electronic component is electronically contacted with the conductive layer.Type: ApplicationFiled: May 5, 2016Publication date: November 10, 2016Applicant: AT & S Austria Technologie & Systemtechnik AktiengesellschaftInventors: Gregor Langer, Johannes Stahr
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Publication number: 20160324004Abstract: A method for embedding a component in a printed circuit board or a printed circuit board intermediate product, wherein the printed circuit board or the printed circuit board intermediate product comprises at least one insulating layer made of a prepreg material, and the component is fixed by the resin of the prepreg material, is characterized by the following steps: providing a combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, wherein this combination includes at least one curable prepreg material; creating a clearance in the combination for accommodating the component to be embedded; covering at least the region of the clearance with a first temporary carrier layer on a first side of the combination; positioning the component to be embedded in the clearance by way of the first temporary carrier layer; covering at least the region of the clearance on the second side of the combination with a second temporary carrier layer; compressing the combinatType: ApplicationFiled: December 12, 2014Publication date: November 3, 2016Applicant: AT&S Austria Technologie & Systemtechnik AktiengesellschaftInventors: Timo Schwarz, Andreas Zluc, Gregor Langer, Johannes Stahr