Patents by Inventor Gregor Langer

Gregor Langer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12652995
    Abstract: A method of manufacturing a semiconductor device in a semiconductor body is proposed. The method includes processing a semiconductor body at a first surface of the semiconductor body. The method further includes attaching the semiconductor body to a carrier via the first surface. The carrier includes an inner part and an outer part at least partly surrounding the inner part. The method further includes processing the semiconductor body at a second surface opposite to the first surface. The method further includes detaching the inner part of the carrier from the semiconductor body.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: June 9, 2026
    Assignee: Infineon Technologies AG
    Inventors: Gregor Langer, Bernhard Goller, Nilesha Mishra, Matteo Piccin, Franz-Josef Pichler
  • Patent number: 12501551
    Abstract: A method for embedding a component in a printed circuit board or a printed circuit board intermediate product, wherein the printed circuit board or the printed circuit board intermediate product comprises at least one insulating layer made of a prepreg material, and the component is fixed by the resin of the prepreg material, is characterized by the following steps: providing a combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, wherein this combination includes at least one curable prepreg material; creating a clearance in the combination for accommodating the component to be embedded; covering at least the region of the clearance with a first temporary carrier layer on a first side of the combination; positioning the component to be embedded in the clearance by way of the first temporary carrier layer; covering at least the region of the clearance on the second side of the combination with a second temporary carrier layer; compressing the combinat
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: December 16, 2025
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Timo Schwarz, Andreas Zluc, Gregor Langer, Johannes Stahr
  • Patent number: 12500086
    Abstract: A method of manufacturing a metal silicide layer comprises performing laser thermal annealing of a surface region of a silicon carbide (SiC) substrate, exposing a surface of a thus obtained silicon layer, depositing a metal layer above the exposed silicon layer, and/or thermally treating a stack of layers, comprising the silicon layer and the metal layer, to form a metal silicide layer. Alternatively and/or additionally, the method may comprise depositing a silicon layer above a SiC substrate, depositing a metal layer, and/or performing laser thermal annealing of the SiC substrate and a stack of layers above the SiC substrate to form a metal silicide layer, wherein the stack of layers comprises the silicon layer and the metal layer. Moreover, a semiconductor device is described, comprising a SiC substrate, a metal silicide layer, and a polycrystalline layer in direct contact with the SiC substrate and the metal silicide layer.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: December 16, 2025
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Hans-Joachim Schulze, Florian Markus Grasse, Moriz Jelinek, Axel König, Gregor Langer, Bernhard Leitl, Kristijan Luka Mletschnig, Werner Schustereder
  • Publication number: 20250266259
    Abstract: A chip is provided. In an embodiment, the chip includes a silicon carbide substrate, a first metal layer on the silicon carbide substrate, and a second metal layer on the first metal layer. The first metal layer and the second metal layer form at least part of an electrical contact. In another embodiment, the chip includes a silicon carbide substrate, a nickel-silicon layer on the silicon carbide substrate, and a layer sequence including a titanium layer, a nickel-containing layer, and a gold-tin or silver layer on the nickel-silicon layer.
    Type: Application
    Filed: May 7, 2025
    Publication date: August 21, 2025
    Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
  • Patent number: 12382585
    Abstract: A method for embedding a component in a printed circuit board or a printed circuit board intermediate product, wherein the printed circuit board or the printed circuit board intermediate product comprises at least one insulating layer made of a prepreg material, and the component is fixed by the resin of the prepreg material, is characterized by the following steps: providing a combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, wherein this combination includes at least one curable prepreg material; creating a clearance in the combination for accommodating the component to be embedded; covering at least the region of the clearance with a first temporary carrier layer on a first side of the combination; positioning the component to be embedded in the clearance by way of the first temporary carrier layer; covering at least the region of the clearance on the second side of the combination with a second temporary carrier layer; compressing the combinat
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: August 5, 2025
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Timo Schwarz, Andreas Zluc, Gregor Langer, Johannes Stahr
  • Publication number: 20250227850
    Abstract: A printed circuit board or a printed circuit board intermediate product, comprises a first main surface and a second main surface; a combination of layers including a plurality of insulating layers and at least one first metal layer, wherein the at least one first metal layer extends along a first horizontal plane in parallel to at least one of the first and second main surfaces; at least one cavity in the printed circuit board or the printed circuit board intermediate product, said cavity extending through at least one of the plurality of insulating layers; and a component inserted in the at least one cavity, said component being embedded in said at least one cavity by a material from the at least one insulating layer through which the cavity extends.
    Type: Application
    Filed: March 28, 2025
    Publication date: July 10, 2025
    Applicant: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Timo Schwarz, Andreas Zluc, Gregor Langer, Johannes Stahr
  • Patent number: 12327727
    Abstract: A chip is provided. In an embodiment, the chip includes a silicon carbide substrate, a first sputtered metal layer on the silicon carbide substrate, and at least one second sputtered metal layer on the first sputtered metal layer. The first sputtered metal layer and the at least one second sputtered metal layer form an electrical contact. In another embodiment, the chip includes a silicon carbide substrate, a nickel-silicon layer on the silicon carbide substrate, and a layer sequence including a titanium layer, a nickel-containing layer, and a gold-tin or silver layer on the nickel-silicon layer.
    Type: Grant
    Filed: August 31, 2023
    Date of Patent: June 10, 2025
    Assignee: Infineon Technologies AG
    Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
  • Publication number: 20240096842
    Abstract: A method for fabricating a SiC power semiconductor device includes: providing a SiC power semiconductor die; depositing a metallization layer over the power semiconductor die, the metallization layer including a first metal; arranging the power semiconductor die over a die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and diffusion soldering the power semiconductor die to the die carrier such that a first intermetallic compound is formed between the power semiconductor die and the plating, the first intermetallic compound including Ni3Sn4.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Ralf Otremba, Gregor Langer, Paul Frank, Alexander Heinrich, Alexandra Ludsteck-Pechloff, Daniel Pedone
  • Publication number: 20240055256
    Abstract: The disclosure relates to a method for manufacturing a contact on a silicon carbide semiconductor substrate and to a silicon carbide semiconductor device comprising a crystalline silicon carbide semiconductor substrate and a contact layer directly in contact with the silicon carbide semiconductor substrate surface and having, at an interface to the semiconductor substrate, a contact phase portion comprising at least a metal, silicon, and carbon. The method comprises the acts of providing a crystalline silicon carbide semiconductor substrate, depositing a metallic contact material layer onto the crystalline silicon carbide semiconductor substrate, and irradiating at least a part of the silicon carbide semiconductor substrate and at least a part of the metallic contact material layer at their interface with at least one thermal annealing laser beam, thereby generating a contact phase portion at the interface, wherein the contact phase portion comprises at least a metal, silicon, and carbon.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 15, 2024
    Inventors: Ravi Keshav JOSHI, Kristijan Luka MLETSCHNIG, Axel KÖNIG, Gregor LANGER
  • Publication number: 20240006218
    Abstract: A method of manufacturing a semiconductor device in a semiconductor body is proposed. The method includes processing a semiconductor body at a first surface of the semiconductor body. The method further includes attaching the semiconductor body to a carrier via the first surface. The carrier includes an inner part and an outer part at least partly surrounding the inner part. The method further includes processing the semiconductor body at a second surface opposite to the first surface. The method further includes detaching the inner part of the carrier from the semiconductor body.
    Type: Application
    Filed: June 20, 2023
    Publication date: January 4, 2024
    Inventors: Gregor Langer, Bernhard Goller, Nilesha Mishra, Matteo Piccin, Franz-Josef Pichler
  • Publication number: 20230420257
    Abstract: A chip is provided. In an embodiment, the chip includes a silicon carbide substrate, a first sputtered metal layer on the silicon carbide substrate, and at least one second sputtered metal layer on the first sputtered metal layer. The first sputtered metal layer and the at least one second sputtered metal layer form an electrical contact. In another embodiment, the chip includes a silicon carbide substrate, a nickel-silicon layer on the silicon carbide substrate, and a layer sequence including a titanium layer, a nickel-containing layer, and a gold-tin or silver layer on the nickel-silicon layer.
    Type: Application
    Filed: August 31, 2023
    Publication date: December 28, 2023
    Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
  • Patent number: 11798807
    Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: October 24, 2023
    Assignee: Infineon Technologies AG
    Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
  • Publication number: 20230317666
    Abstract: A semiconductor device and a method of manufacturing a semiconductor are provided. In an embodiment, a method of manufacturing a semiconductor device is provided. A first layer is formed over a silicon carbide (SiC) layer. The first layer has a first surface distal the SiC layer and a second surface proximal the SiC layer. The first layer includes a metal. First thermal energy may be directed to the first surface of the first layer to form a metal silicide layer from the metal of the first layer and silicon of the SiC layer. The metal silicide layer has a first surface distal the SiC layer and a second surface proximal the SiC layer.
    Type: Application
    Filed: April 4, 2022
    Publication date: October 5, 2023
    Inventors: Gregor Langer, Michael Roesner, Ewald Wiltsche, Ronny Kern, Victorina Poenariu, Axel Koenig
  • Publication number: 20230215729
    Abstract: A method of manufacturing a metal silicide layer comprises performing laser thermal annealing of a surface region of a silicon carbide (SiC) substrate, exposing a surface of a thus obtained silicon layer, depositing a metal layer above the exposed silicon layer, and/or thermally treating a stack of layers, comprising the silicon layer and the metal layer, to form a metal silicide layer. Alternatively and/or additionally, the method may comprise depositing a silicon layer above a SiC substrate, depositing a metal layer, and/or performing laser thermal annealing of the SiC substrate and a stack of layers above the SiC substrate to form a metal silicide layer, wherein the stack of layers comprises the silicon layer and the metal layer. Moreover, a semiconductor device is described, comprising a SiC substrate, a metal silicide layer, and a polycrystalline layer in direct contact with the SiC substrate and the metal silicide layer.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 6, 2023
    Inventors: Hans-Joachim SCHULZE, Florian Markus GRASSE, Moriz JELINEK, Axel KÖNIG, Gregor LANGER, Bemhard LEITL, Kristijan Luka MLETSCHNIG, Werner SCHUSTEREDER
  • Publication number: 20210265168
    Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.
    Type: Application
    Filed: May 10, 2021
    Publication date: August 26, 2021
    Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
  • Publication number: 20210225795
    Abstract: A SiC power semiconductor device includes: a power semiconductor die including SiC and a metallization layer, wherein the metallization layer includes a first metal; a die carrier, wherein the power semiconductor die is arranged over the die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and a first intermetallic compound arranged between the power semiconductor die and the plating and including Ni3Sn4.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 22, 2021
    Inventors: Ralf Otremba, Gregor Langer, Paul Frank, Alexander Heinrich, Alexandra Ludsteck-Pechloff, Daniel Pedone
  • Patent number: 11043383
    Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a chemical cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: June 22, 2021
    Assignee: Infineon Technologies AG
    Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert
  • Publication number: 20200323081
    Abstract: A method for embedding a component in a printed circuit board or a printed circuit board intermediate product, wherein the printed circuit board or the printed circuit board intermediate product comprises at least one insulating layer made of a prepreg material, and the component is fixed by the resin of the prepreg material, is characterized by the following steps: providing a combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, wherein this combination includes at least one curable prepreg material; creating a clearance in the combination for accommodating the component to be embedded; covering at least the region of the clearance with a first temporary carrier layer on a first side of the combination; positioning the component to be embedded in the clearance by way of the first temporary carrier layer; covering at least the region of the clearance on the second side of the combination with a second temporary carrier layer; compressing the combinatio
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Applicant: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Timo Schwarz, Andreas Zluc, Gregor Langer, Johannes Stahr
  • Patent number: 10779413
    Abstract: A method for embedding a component in a printed circuit board or a printed circuit board intermediate product, wherein the printed circuit board or the printed circuit board intermediate product comprises at least one insulating layer made of a prepreg material, and the component is fixed by the resin of the prepreg material, is characterized by the following steps: providing a combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, wherein this combination includes at least one curable prepreg material; creating a clearance in the combination for accommodating the component to be embedded; covering at least the region of the clearance with a first temporary carrier layer on a first side of the combination; positioning the component to be embedded in the clearance by way of the first temporary carrier layer; covering at least the region of the clearance on the second side of the combination with a second temporary carrier layer; compressing the combinatio
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: September 15, 2020
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Timo Schwarz, Andreas Zluc, Gregor Langer, Johannes Stahr
  • Publication number: 20190362973
    Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a chemical cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 28, 2019
    Inventors: Stefan Krivec, Ronny Kern, Stefan Kramp, Gregor Langer, Hannes Winkler, Stefan Woehlert