Patents by Inventor Gregor Nixon
Gregor Nixon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8001509Abstract: A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD—i.e., differences between the devices—are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.Type: GrantFiled: September 19, 2007Date of Patent: August 16, 2011Assignee: Altera CorporationInventors: Steven Perry, Gregor Nixon, Larry Kong, Alasdair Scott, Andrew Hall, Lingli Wang, Chris Dettmar, Jonathan Park, Richard Price
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Patent number: 7530046Abstract: While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes compiling a routing from each internal signal to an output pin. The technology-mapped netlist and placing and routing information corresponding to an original compiled design are saved into a database during full compilation. During debugging, an incremental compiler retrieves this information to build the original routing netlist. The database building, logic synthesis and technology mapping stages may be skipped. New connections are added, fitted to the device, and then the final routing netlist is output into a programming output file (POF) in a form suitable for programming the PLD. The user views the internal signals at the output pins chosen. The user may iterate through this process many times in order to debug the PLD. The debugging assignments may be deleted.Type: GrantFiled: May 18, 2006Date of Patent: May 5, 2009Assignee: Altera CorporationInventors: Gregor Nixon, Mark Jervis, Zhengjun Pan, Gihan De Silva, Steven Perry
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Patent number: 7337101Abstract: A method for designing a system on a programmable logic device (PLD) includes translating a timing requirement of the system into a geographical constraint. Resources on the PLD are fitted onto locations on the PLD in response to the geographical constraint.Type: GrantFiled: April 17, 2003Date of Patent: February 26, 2008Assignee: Altera CorporationInventors: Steven Perry, Gregor Nixon, Ziad Abu-Lebdeh, Alasdair Scott, Philippe Marti
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Publication number: 20080005716Abstract: A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD—i.e., differences between the devices—are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.Type: ApplicationFiled: September 19, 2007Publication date: January 3, 2008Applicant: ALTERA CORPORATIONInventors: Steven Perry, Gregor Nixon, Larry Kong, Alasdair Scott, Andrew Hall, Lingli Wang, Chris Dettmar, Jonathan Park, Richard Price
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Patent number: 7290237Abstract: A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD—i.e., differences between the devices—are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.Type: GrantFiled: June 23, 2004Date of Patent: October 30, 2007Assignee: Altera CorporationInventors: Steven Perry, Gregor Nixon, Larry Kong, Alasdair Scott, Andrew Hall, Lingli Wang, Chris Dettmar, Jonathan Park, Richard Price
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Patent number: 7234125Abstract: Programming software for mask-programmable logic devices provides a timing estimation to the user for the user's logic design during the compilation stage, notwithstanding that the software is not aware of the ultimate placement and routing of the design, which will be performed by the mask-programmable logic device supplier. The software includes a timing model based on actual delay measurements for different user designs in similar devices.Type: GrantFiled: June 23, 2004Date of Patent: June 19, 2007Assignee: Altera CorporationInventors: Alasdair Scott, Gregor Nixon
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Patent number: 7216330Abstract: A method for designing a system on a PLD is disclosed according to a first embodiment of the present invention. A logic design is optimized. Logic circuits from the logic design are mapped to resources on the PLD. At least some of the resources are fitted onto locations on the PLD by utilizing a user-specified procedure.Type: GrantFiled: April 14, 2003Date of Patent: May 8, 2007Assignee: Altera CorporationInventors: Steven Perry, Gregor Nixon, Alasdair Scott, Philippe Marti
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Patent number: 7206967Abstract: While debugging, a user chooses an incremental recompile. Internal signals of interest and output pins are selected, and a number of additional registers are chosen to insert in the path of each internal signal. A clock is selected for the registers. An incremental recompile of the compiled design compiles a routing from each internal signal to an output pin via the added registers. The database building and logic synthesis stages are skipped. The post-fitting logical netlist and routing netlist are retrieved. The new registers are created and the internal signal is connected to the output pin atom in the logical netlist. The fitter places and routes the connections to create a new routing netlist and then the new routing netlist is output into a programming output file (POF) in a form suitable for programming the PLD. The original routing netlist is undisturbed. The user views the internal signals at the output pins chosen. The user may iterate through this process many times in order to debug the PLD.Type: GrantFiled: February 9, 2004Date of Patent: April 17, 2007Assignee: Altera CorporationInventors: Philippe Marti, Mark Jervis, Gregor Nixon
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Patent number: 7076751Abstract: While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes compiling a routing from each internal signal to an output pin. The technology-mapped netlist and placing and routing information corresponding to an original compiled design are saved into a database during full compilation. During debugging, an incremental compiler retrieves this information to build the original routing netlist. The database building, logic synthesis and technology mapping stages may be skipped. New connections are added, fitted to the device, and then the final routing netlist is output into a programming output file (POF) in a form suitable for programming the PLD. The user views the internal signals at the output pins chosen. The user may iterate through this process many times in order to debug the PLD. The debugging assignments may be deleted.Type: GrantFiled: January 24, 2003Date of Patent: July 11, 2006Assignee: Altera CorporationInventors: Gregor Nixon, Mark Jervis, Zhengjun Pan, Gihan De Silva, Steven Perry
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Publication number: 20040261052Abstract: A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD—i.e., differences between the devices—are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.Type: ApplicationFiled: June 23, 2004Publication date: December 23, 2004Applicant: ALTERA CORPORATION, a corporation of DelawareInventors: Steven Perry, Gregor Nixon, Larry Kong, Alasdair Scott, Andrew Hall, Lingli Wang, Chris Dettmar, Jonathan Park, Richard Price