Abstract: An oscillator circuit arrangement includes a switched capacitor circuit at least one capacitor selectively coupled to one of a supply terminal and a terminal for ground potential. A chopper circuit is disposed between the switched capacitor circuit and a comparator. The chopper circuit selectively couples one of input terminals and a reference potential terminal to its output terminals. A buffer circuit is coupled to the output of the comparator circuit. The buffer circuit is connected to the switched capacitor circuit and to the chopper circuit to control selective coupling operations therein.

Abstract: An oscillator circuit includes a first integrator unit to charge a first capacitor at a first integration node, a second integrator unit to charge a second capacitor at a second integration node, a chopped comparator unit and a logic unit. The chopped comparator unit includes comprises a switching unit, a sensing comparator and a replica comparator. The switching unit is configured to couple the first integration node, the second integration node and a reference voltage VREF to the sensing comparator and the replica comparator, depending upon a phase determined by a first input clock signal C1 and a second input clock signal C2, which have opposite phases. The logic unit is configured to generate signals C1, C2, D1, D2, E1, E2 for controlling each integrator unit.

Abstract: A data storage apparatus includes an integrated circuit further including a control unit and a memory array of charge-based memory cells. The memory array includes a first subsection which is operable as a memory, and comprises includes a second subsection which is operable as a dosimeter. The control unit is operable to provide a reference current and to conduct memory access operations to access the memory with reference to the reference current. The control unit is further operable to analyze a statistical distribution of read currents by using memory access operations in the second subsection. Said analysis involves counting of logical read errors of the memory access operations and calibrating the reference current depending on a number of counted logical read errors being indicative also of a Total Ionizing Dose, TID.

Abstract: A memory arrangement comprises a non-volatile memory plane (2), a replacement plane (3), an address select block (302), and a counter arrangement (300) having at least one counter (310 to 312). The at least one counter (310 to 312) is configured to be incremented at a write cycle of the memory arrangement (1). The address select block (302) is configured to switch from the non-volatile memory plane (2) to the replacement plane (3), if a counter value of the at least one counter (310 to 312) is higher than a predetermined limit.

Abstract: A phase-locked loop circuitry (200) having low variation transconductance design comprises a voltage controlled oscillator structure (308) to provide an output signal (Fosc) having an oscillation frequency. The voltage controlled oscillator structure (308) comprises a voltage-to-current converter circuit (312) and a current controlled oscillator circuit (314). The voltage-to-current converter circuit is designed with a low variation transconductance. The voltage-controlled oscillator circuit (200) has a characteristic curve being independent of different PVT (processes, supply voltages and temperature) conditions to ensure that the phase-locked loop circuitry (200) is stable under different PVT condition.

Abstract: A phase-locked loop circuit comprises an oscillator having a plurality of operating curves and being suitable for generating an output signal. In a calibration state the oscillator is trimmed to an operating curve for use in a normal operation state. The phase-locked loop circuit further comprises a phase/frequency detector being suitable for generating at least one error signal based on an input signal and a feedback signal generated on the basis of the output signal. The phase-locked loop circuit further comprises a loop filter being suitable for generating a loop-filter signal based on the at least one error signal, the loop-filter signal being applied to the oscillator in the normal operation state. The phase-locked loop circuit further comprises a calibration circuit being suitable for trimming the oscillator to the operating curve for use in the normal operation state on the basis of the at least one error signal.

Abstract: A phase-locked loop circuit comprises an oscillator having a plurality of operating curves and being suitable for generating an output signal. In a calibration state the oscillator is trimmed to an operating curve for use in a normal operation state. The phase-locked loop circuit further comprises a phase/frequency detector being suitable for generating at least one error signal based on an input signal and a feedback signal generated on the basis of the output signal. The phase-locked loop circuit further comprises a loop filter being suitable for generating a loop-filter signal based on the at least one error signal, the loop-filter signal being applied to the oscillator in the normal operation state. The phase-locked loop circuit further comprises a calibration circuit being suitable for trimming the oscillator to the operating curve for use in the normal operation state on the basis of the at least one error signal.

Abstract: The PLL circuit comprises a phase/frequency detector (302), a loop filter (304, 306), a VCO (308) and a feedback loop (320). The VCO can be electrically disconnected from the PLL and comprises a programmable trimming circuit (316) and a current-controlled oscillator (318). For calibration the VCO is electrically disconnected from the loop filter and from the feedback loop, a constant reference voltage is applied to the voltage input (IN), a center frequency programming code (L) is applied to the trimming circuit, the center frequency programming code is iteratively adjusted until a desired center frequency is obtained, a gain programming code (K) is applied to the trimming circuit while the adjusted code is still applied, and the gain programming code is iteratively adjusted until a desired gain is obtained. Then the VCO is connected to the PLL, which is then ready for normal operation.

Abstract: The oscillator circuit comprises first and second integrator units with a first capacitor charged at a first integration node and a second capacitor charged at a second integration node. A comparator unit is arranged between a first switching unit, which is connected to the integration nodes and to a reference signal (VREF), and a second switching unit. The comparator unit compares a signal from the first or second integration node with the reference signal. The second switching unit is connected to a logic unit configured to provide signals controlling the first integrator unit, the second integrator unit, the first switching unit and the second switching unit, so that a periodic operation is generated by alternatingly activating the first integrator unit and the second integrator unit.

Abstract: A phase-locked loop circuitry (200) having low variation transconductance design comprises a voltage controlled oscillator structure (308) to provide an output signal (Fosc) having an oscillation frequency. The voltage controlled oscillator structure (308) comprises a voltage-to-current converter circuit (312) and a current controlled oscillator circuit (314). The voltage-to-current converter circuit is designed with a low variation transconductance. The voltage-controlled oscillator circuit (200) has a characteristic curve being independent of different PVT (processes, supply voltages and temperature) conditions to ensure that the phase-locked loop circuitry (200) is stable under different PVT condition.

Abstract: In an embodiment an oscillator circuit comprises a first integrator-comparator unit, a second integrator-comparator unit, and a logic circuit. The first integrator-comparator unit is prepared to provide a first signal as a function of a first integration of a first charging current and a subsequent comparison of a first integration signal resulting from the first integration with a reference signal. The second integrator-comparator unit is prepared to provide a third signal as a function of a second integration of a second charging current and a subsequent comparison of a second integration signal resulting from the second integration with the reference signal. The logic circuit is adapted to provide a clock signal, a first and a second measurement signal for respectively controlling the first and the second integrator-comparator unit.

Abstract: The oscillator circuit comprises first and second integrator units with a first capacitor charged at a first integration node and a second capacitor charged at a second integration node. A comparator unit is arranged between a first switching unit, which is connected to the integration nodes and to a reference signal (VREF), and a second switching unit. The comparator unit compares a signal from the first or second integration node with the reference signal. The second switching unit is connected to a logic unit configured to provide signals controlling the first integrator unit, the second integrator unit, the first switching unit and the second switching unit, so that a periodic operation is generated by alternatingly activating the first integrator unit and the second integrator unit.

Abstract: A memory arrangement comprises a non-volatile memory plane (2), a replacement plane (3), an address select block (302), and a counter arrangement (300) having at least one counter (310 to 312). The at least one counter (310 to 312) is configured to be incremented at a write cycle of the memory arrangement (1). The address select block (302) is configured to switch from the non-volatile memory plane (2) to the replacement plane (3), if a counter value of the at least one counter (310 to 312) is higher than a predetermined limit.

Abstract: In an embodiment an oscillator circuit comprises a first integrator-comparator unit, a second integrator-comparator unit, and a logic circuit. The first integrator-comparator unit is prepared to provide a first signal as a function of a first integration of a first charging current and a subsequent comparison of a first integration signal resulting from the first integration with a reference signal. The second integrator-comparator unit is prepared to provide a third signal as a function of a second integration of a second charging current and a subsequent comparison of a second integration signal resulting from the second integration with the reference signal. The logic circuit is adapted to provide a clock signal, a first and a second measurement signal for respectively controlling the first and the second integrator-comparator unit.

Abstract: The PLL circuit comprises a phase/frequency detector (302), a loop filter (304, 306), a VCO (308) and a feedback loop (320). The VCO can be electrically disconnected from the PLL and comprises a programmable trimming circuit (316) and a current-controlled oscillator (318). For calibration the VCO is electrically disconnected from the loop filter and from the feedback loop, a constant reference voltage is applied to the voltage input (IN), a center frequency programming code (L) is applied to the trimming circuit, the center frequency programming code is iteratively adjusted until a desired center frequency is obtained, a gain programming code (K) is applied to the trimming circuit while the adjusted code is still applied, and the gain programming code is iteratively adjusted until a desired gain is obtained. Then the VCO is connected to the PLL, which is then ready for normal operation.

Abstract: The present invention relates to an oscillator circuit, comprising a switched capacitor circuit comprising a parallel circuit with a current input to be supplied with a reference current on one side and being connected to a reference terminal on the other side. The parallel circuit further comprises a first capacitor in a first branch and, in a second branch, a second capacitor connected in-between a first and second switch. A switch control unit comprises a first input coupled to the current input of the parallel circuit and a second input to be supplied with a reference voltage as well as an oscillator output for providing an oscillator signal. The switch control unit is being designed to operate the first and second switch such that, in a charging phase, the first and second capacitor is charged to a respective level depending on the reference voltage and, in a discharging phase, the charge stored on the first capacitor is discharged using the charge stored on the second capacitor.

Abstract: An oscillator circuit comprises a current path including a capacitor having a first side and a second side, wherein each of the first and second side of the capacitor is selectively connectable to at least a first supply terminal to apply a first voltage potential or a second supply terminal to apply a second voltage potential. The oscillator circuit comprises a comparator having a first input terminal being selectively connectable to the first or the second side of the capacitor, and a second input terminal being connected to a terminal to apply a reference voltage. An output signal of the oscillator circuit is generated in dependence on a comparator output signal of the comparator.

Abstract: The present invention relates to an oscillator circuit, comprising a switched capacitor circuit comprising a parallel circuit with a current input to be supplied with a reference current on one side and being connected to a reference terminal on the other side. The parallel circuit further comprises a first capacitor in a first branch and, in a second branch, a second capacitor connected in-between a first and second switch. A switch control unit comprises a first input coupled to the current input of the parallel circuit and a second input to be supplied with a reference voltage as well as an oscillator output for providing an oscillator signal. The switch control unit is being designed to operate the first and second switch such that, in a charging phase, the first and second capacitor is charged to a respective level depending on the reference voltage and, in a discharging phase, the charge stored on the first capacitor is discharged using the charge stored on the second capacitor.

Abstract: An oscillator circuit (10) comprises a current path (100) including a capacitor (110) having a first side (S110a) and a second side (S110b), wherein each of the first and second side (S110a, S110b) of the capacitor (110) is selectively connectable to at least a first supply terminal (VD) to apply a first voltage potential (VDDA) or a second supply terminal (VS) to apply a second voltage potential (VSS). The oscillator circuit (10) comprises a comparator (200) having a first input terminal (I200a) being selectively connectable to the first or the second side (S110a, S110b) of the capacitor (110), and a second input terminal (I200b) being connected to a terminal (VR) to apply a reference voltage (VREF). An output signal (OUT, OUTB) of the oscillator circuit is generated in dependence on a comparator output signal (VCFF) of the comparator (200).

Abstract: A charge pump circuit (11) comprises a first stage (31) and at least a second stage (32), each having a capacitor (130, 230) and a current source (100, 200). The charge pump circuit (11) is configured such that, in a first phase (A) of operation, the capacitor (130) of the first stage (31) is switched in series to the current source (100) of the first stage (31) and the capacitor (230) of the second stage (32) is switched in series to the current source (200) of the second stage (32) and that, in a second phase (B) of operation, the capacitor (130) of the first stage (31) and the capacitor (230) of the second stage (32) are switched in series for providing a supply voltage (VHF) at an output (15) of the charge pump circuit (11). A comparator signal (SCOM) is generated by comparing a voltage at an electrode of one of the capacitors (130, 230) of the first and the at least second stage (31, 32) with a reference voltage (VR).