Patents by Inventor Gregorio Gervasio
Gregorio Gervasio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11750522Abstract: Systems and methods of communicating in a network use rate limiting. Rate limiting units (either receive side or transmit side) can perform rate limiting in response to a) a maximum number of bytes that can be solicited over a first period of time is exceeded, b) a maximum number of bytes that are outstanding over a second period of time is exceeded; or c) a maximum number of commands that are outstanding over a period of time is exceeded as part of CMD_RXRL. The CMD_RXRL can have three components (a) max bytes, b) outstanding bytes, c) outstanding commands. TXRL contains the component of max bytes or maximum number of bytes that can be transmitted over a third period of time to match the speed of a receive link, or any node or link through the network/fabric.Type: GrantFiled: April 19, 2021Date of Patent: September 5, 2023Assignee: Avago Technologies International Sales Pte. LimitedInventors: Kenny Wu, James Winston Smart, Mark Karnowski, Ravi Shenoy, Gregorio Gervasio, Jr., Lalit Chhabra, Chakradhara Raj Yadav Aradhyula
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Publication number: 20220337524Abstract: Systems and methods of communicating in a network use rate limiting. Rate limiting units (either receive side or transmit side) can perform rate limiting in response to a) a maximum number of bytes that can be solicited over a first period of time is exceeded, b) a maximum number of bytes that are outstanding over a second period of time is exceeded; or c) a maximum number of commands that are outstanding over a period of time is exceeded as part of CMD_RXRL. The CMD_RXRL, can have three components (a) max bytes, b) outstanding bytes, c) outstanding commands. TXRL, contains the component of max bytes or maximum number of bytes that can be transmitted over a third period of time to match the speed of a receive link, or any node or link through the network/fabric.Type: ApplicationFiled: April 19, 2021Publication date: October 20, 2022Inventors: Kenny Wu, James Winston Smart, Mark Karnowski, Ravi Shenoy, Gregorio Gervasio, JR., Lalit Chhabra, Chakradhara Raj Yadav Aradhyula
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Publication number: 20220334985Abstract: Systems and methods relate to a bus adapter for a storage network. The bus adaptor includes a context memory comprising a first storage for uncacheable exchange resource indicators (XRI) and a second storage for cacheable XRI. The bus adapter also includes a host backing store unit configured to provide access to the different tier memories present locally or externally in the host memory extension using several caching sub-units and with the capability of an optional pinning operation for the cacheable XRI based upon at least one of input/output phase, first in line up to a limit, a region of a virtual context address associated with the cacheable XRI indicators, a protocol associated with the cacheable XRI, a size of a transaction, or work queue information.Type: ApplicationFiled: April 16, 2021Publication date: October 20, 2022Inventors: Marc Pegolotti, Kenny Wu, Ravi Shenoy, Gregorio Gervasio, JR., Lalit Chhabra, Mark Karnowski, James Winston Smart, Vuong Cao Nguyen
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Patent number: 10996980Abstract: A number of command processing devices, architectures, and methods are described. One example of a command processing device is disclosed to include a classification engine configured to classify input commands, a sequencer in communication with the classification engine, one or more thread managers in communication with the sequencer, and one or more sub-processing engines in communication with each of the one or more thread managers. The sequencer may control staging of work across multiple threads and processing elements within threads. Each of the one or more thread managers are configured to delegate work to different sub-processing engines. Each of the one or more sub-processing engines are configured to perform sub-tasks in connection with completing processing of an input command received at the classification engine based on particular sub-tasks assigned to the one or more sub-processing engines by the one or more thread managers.Type: GrantFiled: April 23, 2018Date of Patent: May 4, 2021Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Lalit Chhabra, Gregorio Gervasio, Jr., Kenny Wu, Mark Karnowski
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Patent number: 10735340Abstract: A networking adaptor and method of transferring data are depicted and described herein. One example of the networking adaptor is provided with a host interface and a network interface. The network interface may include a transmit portion and a receive portion. The transmit portion may include a first set of data paths and the receive portion may include a second set of data paths. Both the first set of data paths and second set of data paths are configurable to be aggregated or de-aggregated to support a single port operation that represents a combined bandwidth of the data paths in the first set of data paths or the second set of data paths.Type: GrantFiled: April 18, 2018Date of Patent: August 4, 2020Assignee: Avago Technologies International Sales Pte. LimitedInventors: Kenny Wu, Gregorio Gervasio, Jr., Lalit Chhabra, Ravi Shenoy
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Patent number: 10664420Abstract: A system, method, and adaptor that facilitate data transmission are described. One example of the disclosed system facilitates the chip-to-chip transport of header descriptors and payloads. The system may include a source chip, a destination chip, and a set of queues describing buffer memory locations for staging header descriptors and payloads to be transferred from the source chip to the destination chip, where the set of queues are directly accessible to the source chip and to the destination chip.Type: GrantFiled: April 19, 2018Date of Patent: May 26, 2020Assignee: Avago Technologies International Sales Pte. LimitedInventors: Kenny Wu, Mark Karnowski, James Smart, Ravi Shenoy, Lalit Chhabra, Gregorio Gervasio, Jr., Tuong Le, Vuong Nguyen
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Publication number: 20190327178Abstract: A networking adaptor and method of transferring data are depicted and described herein. One example of the networking adaptor is provided with a host interface and a network interface. The network interface may include a transmit portion and a receive portion. The transmit portion may include a first set of data paths and the receive portion may include a second set of data paths. Both the first set of data paths and second set of data paths are configurable to be aggregated or de-aggregated to support a single port operation that represents a combined bandwidth of the data paths in the first set of data paths or the second set of data paths.Type: ApplicationFiled: April 18, 2018Publication date: October 24, 2019Inventors: Kenny Wu, Gregorio Gervasio, JR., Lalit Chhabra, Ravi Shenoy
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Publication number: 20190324926Abstract: A system, method, and adaptor that facilitate data transmission are described. One example of the disclosed system facilitates the chip-to-chip transport of header descriptors and payloads. The system may include a source chip, a destination chip, and a set of queues describing buffer memory locations for staging header descriptors and payloads to be transferred from the source chip to the destination chip, where the set of queues are directly accessible to the source chip and to the destination chip.Type: ApplicationFiled: April 19, 2018Publication date: October 24, 2019Inventors: Kenny Wu, Mark Karnowski, James Smart, Ravi Shenoy, Lalit Chhabra, Gregorio Gervasio, JR., Tuong Le, Vuong Nguyen
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Publication number: 20190324800Abstract: A number of command processing devices, architectures, and methods are described. One example of a command processing device is disclosed to include a classification engine configured to classify input commands, a sequencer in communication with the classification engine, one or more thread managers in communication with the sequencer, and one or more sub-processing engines in communication with each of the one or more thread managers. The sequencer may control staging of work across multiple threads and processing elements within threads. Each of the one or more thread managers are configured to delegate work to different sub-processing engines. Each of the one or more sub-processing engines are configured to perform sub-tasks in connection with completing processing of an input command received at the classification engine based on particular sub-tasks assigned to the one or more sub-processing engines by the one or more thread managers.Type: ApplicationFiled: April 23, 2018Publication date: October 24, 2019Inventors: Lalit Chhabra, Gregorio Gervasio, JR., Kenny Wu, Mark Karnowski
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Patent number: 7548996Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.Type: GrantFiled: September 12, 2005Date of Patent: June 16, 2009Assignees: Hitachi, Ltd., Equator Technologies, Inc.Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee, Yatin Mundkur, Toru Nojiri, John O'Donnell, John Poole, legal representative, Ashok Raman, Eric Rehm, Radhika Thekkath, David Poole
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Patent number: 7457890Abstract: An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.Type: GrantFiled: October 30, 2006Date of Patent: November 25, 2008Assignee: Hitachi, Ltd.Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Patent number: 7272670Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. A processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the processor and the data transfer switch. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. As interface unit is coupled to the data streamer and has a plurality of I/O device driver units. A multiplexer coupled to the interface unit provides access between a selected number of I/O device driver units and external I/O devices via output pins.Type: GrantFiled: February 5, 2001Date of Patent: September 18, 2007Assignee: HitachiInventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Publication number: 20070130401Abstract: An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.Type: ApplicationFiled: October 30, 2006Publication date: June 7, 2007Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Publication number: 20060288134Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.Type: ApplicationFiled: September 12, 2005Publication date: December 21, 2006Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee, Yatin Mundkur, Toru Nojiri, John O'Donnell, David Poole, Ashok Raman, Eric Rehm, Radhika Thekkath, John Poole
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Patent number: 7051123Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.Type: GrantFiled: November 10, 2000Date of Patent: May 23, 2006Assignees: Hitachi, Ltd., Equator Technologies, Inc.,Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee, Yatin Mundkur, Toru Nojiri, John O'Donnell, Ashok Raman, Eric Rehm, Radhika Thekkath
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Publication number: 20040255058Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations.Type: ApplicationFiled: June 15, 2004Publication date: December 16, 2004Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Publication number: 20040221071Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations.Type: ApplicationFiled: February 5, 2001Publication date: November 4, 2004Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Publication number: 20030196040Abstract: An information processing system has a plurality of modules, including a processor, a main memory and a plurality of I/O devices. A data cache comprises a cache data memory which is coupled to the processor which provides data to the processor in response to a load operation and for writing data from the processor in response to a store operation. A refill controller is coupled to the cache data memory for controlling the operation of the data cache in accordance with a specifiable policy. An external access controller is coupled to the cache data memory. The external access controller is coupled to an external memory bus, such that the contents of the cache data memory are accessible for read and write operations in response to read and write requests issued by the modules in the information processing system.Type: ApplicationFiled: December 18, 2002Publication date: October 16, 2003Inventors: Koji Hosogi, Gregorio Gervasio, Yatin Mundkur, Radhika Thekkath
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Patent number: 6560674Abstract: An information processing system has a plurality of modules, including a processor, a main memory and a plurality of I/O devices. A data cache comprises a cache data memory which is coupled to the processor which provides data to the processor in response to a load operation and for writing data from the processor in response to a store operation. A refill controller is coupled to the cache data memory for controlling the operation of the data cache in accordance with a specifiable policy. An external access controller is coupled to the cache data memory. The external access controller is coupled to an external memory bus, such that the contents of the cache data memory are accessible for read and write operations in response to read and write requests issued by the modules in the information processing system.Type: GrantFiled: October 14, 1998Date of Patent: May 6, 2003Assignees: Hitachi, Ltd., Equater Technologies, Inc.Inventors: Koji Hosogi, Gregorio Gervasio, Yatin Mundkur, Radhika Thekkath
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Patent number: 6434649Abstract: In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices.Type: GrantFiled: October 14, 1998Date of Patent: August 13, 2002Assignees: Hitachi, Ltd., Equator TechnologiesInventors: David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee, Yatin Mundkur, Toru Nojiri, John O'Donnell, David Poole, Ashok Raman, Eric Rehm, Radhika Thekkath