Patents by Inventor Gregorio Murtagian
Gregorio Murtagian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230197594Abstract: An electronic system and associated methods are disclosed. In one example, the electronic system includes a processor package including at least one processor integrated circuit (IC); an interposer including electrically conductive interposer interconnect; a first liquid metal well array including multiple liquid metal wells arranged between the processor package and the interposer, wherein the first liquid metal well array is attached to a surface of the processor package and attached to a first surface of the interposer and the interposer interconnect; a printed circuit board (PCB) attached to a second surface of the interposer and the interposer interconnect; a second liquid metal well array including a first surface attached to the first surface of the interposer and the interposer interconnect; and a first companion component package attached to a second surface of the second liquid metal well array.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Inventors: Karumbu Meyyappan, Jeffory L. Smalley, Gregorio Murtagian, Srikant Nekkanty, Eric J.M. Moret, Pooya Tadayon
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Publication number: 20230197622Abstract: An electronic system and associated methods are disclosed. In one example, the electronic system includes an interposer including electrically conductive interposer interconnect, a first interposer surface, and a second interposer surface; a processor package including at least one processor integrated circuit (IC), the processor package attached to the first interposer surface and electrically connected to the interposer interconnect; a first liquid metal well array including multiple liquid metal wells attached to a second interposer surface and the interposer interconnect; a second liquid metal well array including a first array surface attached to the first interposer surface and the interposer interconnect; and a packaged companion IC to the processor IC attached to a second array surface of the second liquid metal well array.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Inventors: Karumbu Meyyappan, Jeffory L, Smalley, Gregorio Murtagian, Srikant Nekkanty, Pooya Tadayon, Eric J.M. Moret, Bijoyraj Sahu
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Publication number: 20230197621Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an integrated circuit (IC) package substrate including package interconnect and a first substrate surface; a processor IC attached to the first substrate surface and electrically connected to the package interconnect; a liquid metal well array including multiple liquid metal wells, a first array surface attached to the first substrate surface, and a second array surface; and a companion component to the processor IC attached to the second array surface of the liquid metal well array.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Inventors: Karumbu Meyyappan, Jeffory L. Smalley, Gregorio Murtagian, Srikant Nekkanty, Eric J.M. Moret, Pooya Tadayon
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Publication number: 20230187850Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a socket that includes one or more liquid metal filled reservoirs. In selected examples, the electronic devices and sockets include configurations to aid in reducing ingress of moisture.Type: ApplicationFiled: December 13, 2021Publication date: June 15, 2023Inventors: Ziyin Lin, Aaron Michael Garelick, Karumbu Meyyappan, Gregorio Murtagian, Srikant Nekkanty, Taylor Rawlings, Jeffory L. Smalley, Pooya Tadayon, Dingying Xu
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Publication number: 20230187337Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes liquid metal pathways that form one or more conduction pathway through one or more dielectric layers. In selected examples, the dielectric layers are resilient, which allows for flexibility of interconnect components.Type: ApplicationFiled: December 14, 2021Publication date: June 15, 2023Inventors: Karumbu Meyyappan, Srikant Nekkanty, Gregorio Murtagian, Pooya Tadayon, Ziyin Lin, Eric J.M. Moret, Jeffory L. Smalley, Dingying Xu
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Patent number: 10522450Abstract: An electronic device may include a semiconductor package, that may include a package substrate. The package may include a semiconductor die. A plurality of package interconnects may include a first pillar extending from a surface of the package substrate. The electronic device may include a socket that may be configured to couple with the semiconductor package. The socket may include a plurality of socket interconnects configured to engage with the package interconnects. The plurality of socket interconnects may include a first contact, and the first contact may include an arm. The arm of the first contact may be configured to engage with the first pillar, and the arm may be configured to laterally displace when engaged with the first pillar. The engagement of the arm with the first pillar may establish an electrical communication pathway between the semiconductor package and the socket.Type: GrantFiled: October 15, 2018Date of Patent: December 31, 2019Assignee: Intel CorporationInventors: Gregorio Murtagian, Saikumar Jayaraman
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Patent number: 10044115Abstract: An apparatus comprises a cable connector including: a first connector body portion including a first plurality of electrical contacts arranged to contact electrical contacts of a first surface of an edge connector substrate; a second connector body portion separate from the first connector body portion and including a second plurality of electrical contacts arranged to oppose the first plurality of electrical contacts of the first connector body portion and to contact electrical contacts of a second surface of the edge connector substrate, wherein the first and second plurality of electrical contacts are electrically coupled to one or more cables; and a joining mechanism configured to join the first connector body portion and the second connector body portion together and to apply a bias force to the edge connector substrate when the edge connector substrate is arranged between the first connector body portion and the second connector body portion.Type: GrantFiled: December 23, 2015Date of Patent: August 7, 2018Assignee: Intel CorporationInventors: Donald T. Tran, Gregorio Murtagian, Kuang Liu, Srikant Nekkanty, Feroz Mohammad, Karumbu Meyyappan, Hong Xie, Russell S. Aoki, Gaurav Chawla
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Publication number: 20170187147Abstract: An apparatus comprises a cable connector including: a first connector body portion including a first plurality of electrical contacts arranged to contact electrical contacts of a first surface of an edge connector substrate; a second connector body portion separate from the first connector body portion and including a second plurality of electrical contacts arranged to oppose the first plurality of electrical contacts of the first connector body portion and to contact electrical contacts of a second surface of the edge connector substrate, wherein the first and second plurality of electrical contacts are electrically coupled to one or more cables; and a joining mechanism configured to join the first connector body portion and the second connector body portion together and to apply a bias force to the edge connector substrate when the edge connector substrate is arranged between the first connector body portion and the second connector body portion.Type: ApplicationFiled: December 23, 2015Publication date: June 29, 2017Inventors: Donald T. Tran, Gregorio Murtagian, Kuang Liu, Srikant Nekkanty, Feroz Mohammad, Karumbu Meyyappan, Hong Xie, Russell S. Aoki, Gaurav Chawla
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Patent number: 9603276Abstract: Some forms relate to an electronic assembly that includes a plurality of electronic package. The electronic assembly includes a frame and a first electronic package mounted on the frame. The first electronic package includes a first pin grid array. The electronic assembly further includes a second electronic package mounted on the frame. The second electronic package includes a second pin grid array. The electronic assembly further includes an actuation mechanism on the frame. The actuation mechanism is configured to move the first electronic package and the second electronic package relative to the frame during operation of the actuation mechanism.Type: GrantFiled: December 26, 2014Date of Patent: March 21, 2017Assignee: Intel CorporationInventors: David J. Llapitan, Jeffory L. Smalley, Gaurav Chawla, Joshua D Heppner, Vijaykumar Krithivasan, Jonathan W. Thibado, Kuang Liu, Gregorio Murtagian
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Publication number: 20160190717Abstract: Some forms relate to an electronic assembly that includes a plurality of electronic package. The electronic assembly includes a frame and a first electronic package mounted on the frame. The first electronic package includes a first pin grid array. The electronic assembly further includes a second electronic package mounted on the frame. The second electronic package includes a second pin grid array. The electronic assembly further includes an actuation mechanism on the frame. The actuation mechanism is configured to move the first electronic package and the second electronic package relative to the frame during operation of the actuation mechanism.Type: ApplicationFiled: December 26, 2014Publication date: June 30, 2016Inventors: David J. Llapitan, Jeffory L. Smalley, Gaurav Chawla, Joshua D. Heppner, Vijaykumar Krithivasan, Jonathan W. Thibado, Kuang Liu, Gregorio Murtagian
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Publication number: 20160190716Abstract: Some forms relate to a socket having a housing. A first receiving pin field is formed as part of the housing. The first pin receiving field includes a first plurality of electrical contacts. A second receiving pin field is formed as part of the housing. The second pin field includes a second plurality of electrical contacts. An actuation mechanism is configured to engage the first plurality electrical contacts with a first set of pins on a first electronic package and the second plurality electrical contacts with a second set of pins on a second electronic package.Type: ApplicationFiled: December 26, 2014Publication date: June 30, 2016Inventors: Kuang Liu, Gregorio Murtagian, David J. Llapitan, Jeffory L. Smalley, Gaurav Chawla, Joshua D. Heppner, Vijaykumar Krithivasan, Jonathan W. Thibado