Patents by Inventor Gregorio R. Murtagian

Gregorio R. Murtagian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220386457
    Abstract: An electronic device carrier structure can include a substrate including a plurality of electrical contacts spaced apart on the substrate, a plurality of electrically conductive balls, each of the electrically conductive balls being on a respective one of the plurality of electrical contacts, solder attaching each of the electrically conductive balls to respective ones of the electrical contacts to form an attachment boundary where the solder ends on a surface of each of the plurality of electrically conductive balls, and a polymer layer extending on the substrate onto the plurality of electrically conductive balls to form a surface of the polymer layer at a contact point on the plurality of electrically conductive balls that is above the attachment boundary and below an apex of each of the plurality of electrically conductive balls.
    Type: Application
    Filed: May 21, 2022
    Publication date: December 1, 2022
    Inventors: Omkar Gupte, Vanessa Smet, Gregorio R. Murtagian
  • Publication number: 20220308294
    Abstract: Embodiments disclosed herein include photonics packages and systems. In an embodiment, a photonics package comprises a package substrate, where the package substrate comprises a cutout along an edge of the package substrate. In an embodiment, a photonics die is coupled to the package substrate, and the photonics die is positioned adjacent to the cutout. In an embodiment, the photonics package further comprises a receptacle for receiving a pluggable optical connector. In an embodiment, the receptacle is over the cutout.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Inventors: Wesley MORGAN, Srikant NEKKANTY, Todd R. COONS, Gregorio R. MURTAGIAN, Xiaoqian LI, Nitin DESHPANDE, Divya PRATAP
  • Publication number: 20220183177
    Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 9, 2022
    Inventors: Zhichao ZHANG, Gregorio R. MURTAGIAN, Kuang C. LIU, Kemal AYGUN
  • Patent number: 11291133
    Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Zhichao Zhang, Gregorio R. Murtagian, Kuang C Liu, Kemal Aygun
  • Publication number: 20210307153
    Abstract: Embodiments disclosed herein include assemblies. In an embodiment, an assembly comprises a socket and a bolster plate on a board, where the bolster plate has load studs and an opening that surrounds the socket; a shim having first and second ends; and a carrier on the bolster plate, where the carrier has an opening and cutouts. The shim may have an opening through the first end as the second end is affixed to the carrier. The opening of the shim entirely over one cutout from a corner region of the carrier. In an embodiment, the assembly comprises an electronic package in the opening of the carrier, where the electronic package is affixed to the carrier, and a heatsink over the electronic package and carrier, where the first end is directly coupled to a surface of the heatsink and a surface of one load stud of the bolster plate.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Inventors: Feroz MOHAMMAD, Ralph V. MIELE, Thomas BOYD, Steven A. KLEIN, Gregorio R. MURTAGIAN, Eric W. BUDDRIUS, Daniel NEUMANN, Rolf LAIDO
  • Publication number: 20200335432
    Abstract: A circuit board assembly includes at least one circuit board having a plurality of conductive layers, the at least one circuit board having a first face and an opposite second face. A first chip socket on the first face is positioned opposite of a second chip socket on the second face. In one example, each chip socket can receive a processor. The first and second chip sockets may be arranged in a mirrored fashion with respect to one another, or an overlapping but non-mirrored fashion. In any such arrangements, as fasteners are tightened to fully seat first and second chips respectively installed in the first and second chip sockets, forces applied to the first chip effectively neutralize or otherwise reduce opposing forces applied to the second chip, thereby reducing circuit board deflection.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Gregorio R. Murtagian, Jeffory L. Smalley, Thomas T. Holden, Silver A. Estrada Rodriguez, Luis E. Rosales Galvan
  • Publication number: 20200066659
    Abstract: A microelectronics package, comprising a substrate comprising a first bondpad and a second bondpad over a dielectric. An inductor comprising at least one wire extends over the dielectric. The at least one wire has a first end coupled to the first bondpad and a second end coupled to the second bondpad, and an inductor core layer over the dielectric. The inductor core layer comprises a magnetic material. At least a portion of the inductor extends within the inductor core layer.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Applicant: Intel Corporation
    Inventors: William J. Lambert, Omkar Karhade, Martin Rodriguez, Gregorio R. Murtagian
  • Publication number: 20190307009
    Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Inventors: Zhichao ZHANG, Gregorio R. MURTAGIAN, Kuang C. LIU, Kemal AYGUN
  • Patent number: 10431912
    Abstract: High-speed data transmissions through a CPU socket are facilitated with CPU socket contacts that have a CPU socket contact body that improves bandwidth throughput. The CPU socket contact body is partially suspended from a CPU socket contact and may include a cavity. The CPU socket contact body includes capacitive impedance that substantially cancels an inductive impedance of the CPU socket contact. Canceling the inductive impedance causes the CPU socket contact to operate like an impedance-matched coaxial transmission line, which enables better bandwidth throughput than a non-impedance matched transmission line.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Gregorio R. Murtagian, Zhichao Zhang
  • Patent number: 10396036
    Abstract: A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia).
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Yu Amos Zhang, Zhiguo Qian, Kemal Aygun, Yidnekachew S. Mekonnen, Gregorio R. Murtagian, Sanka Ganesan, Eduard Roytman, Jeff C. Morriss
  • Publication number: 20190182955
    Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a package substrate. The electronic device package can also include a processor mounted on the package substrate. Additionally, the electronic device package can include a memory socket mounted on the package substrate and operably coupled to the processor. The memory socket can be operable to removably couple with a memory module and facilitate electrical communication between the processor and the memory module. A memory module can include a plurality of printed circuit boards (PCBs). Each PCB can have a bottom edge and a plurality of contact pads located about the bottom edge. Additionally, the memory module can include a memory device mounted on at least one of the plurality of PCBs and electrically connected to at least one of the pluralities of contact pads to facilitate electrically coupling the memory module with an external electronic component, such as a processor.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 13, 2019
    Applicant: Intel Corporation
    Inventors: Gregorio R. Murtagian, Kuang C. Liu, Sriram Srinivasan, Jeffory L. Smalley, Zhichao Zhang
  • Patent number: 10321573
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations to provide solder contacts for electrical connection in socket assemblies. In one embodiment, a solder contact may be disposed on the bottom surface of a die package such that the solder contact is conductively coupled to electrical contacts of the die package. The solder contacts may be disposed to be coupled to pins of a socket assembly, to provide conductive coupling of the electrical contacts of the die package and the pins of the socket assembly. The solder may be selected to be sufficiently soft to provide for better electrical conduction. The pins may also be configured to penetrate the solder contact to provide for better electrical conduction. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 11, 2019
    Assignee: INTEL CORPORATION
    Inventors: Fay Hua, Hong Xie, Gregorio R. Murtagian, Amit Abraham, Alan C. McAllister, Ting Zhong
  • Publication number: 20190103687
    Abstract: High-speed data transmissions through a CPU socket are facilitated with CPU socket contacts that have a CPU socket contact body that improves bandwidth throughput. The CPU socket contact body is partially suspended from a CPU socket contact and may include a cavity. The CPU socket contact body includes capacitive impedance that substantially cancels an inductive impedance of the CPU socket contact. Canceling the inductive impedance causes the CPU socket contact to operate like an impedance-matched coaxial transmission line, which enables better bandwidth throughput than a non-impedance matched transmission line.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Applicant: Intel Corporation
    Inventors: GREGORIO R. MURTAGIAN, ZHICHAO ZHANG
  • Publication number: 20180331043
    Abstract: A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia).
    Type: Application
    Filed: December 26, 2015
    Publication date: November 15, 2018
    Inventors: Yu Amos ZHANG, Zhiguo QIAN, Kemal AYGUN, Yidnekachew S. MEKONNEN, Gregorio R. MURTAGIAN, Sanka GANESAN, Eduard ROYTMAN, Jeff C. MORRISS
  • Patent number: 10056182
    Abstract: Embodiments of the present disclosure are directed towards an inductor structure having one or more strips of conductive material disposed around a core. The strips may have contacts at a first end and a second end of the strips, and may be disposed around the core with a gap between the contacts. The inductor structure may be mounted on a surface of a substrate, and one or more traces may be formed in the surface of the substrate to electrically couple two or more of the strips of conductive material to one another to form inductive coils. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: August 21, 2018
    Assignee: Intel Corporation
    Inventors: Gregorio R. Murtagian, Robert L. Sankman, Brent S. Stone, Kaladhar Radhakrishnan, Joshua D. Heppner
  • Publication number: 20180192519
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations to provide solder contacts for electrical connection in socket assemblies. In one embodiment, a solder contact may be disposed on the bottom surface of a die package such that the solder contact is conductively coupled to electrical contacts of the die package. The solder contacts may be disposed to be coupled to pins of a socket assembly, to provide conductive coupling of the electrical contacts of the die package and the pins of the socket assembly. The solder may be selected to be sufficiently soft to provide for better electrical conduction. The pins may also be configured to penetrate the solder contact to provide for better electrical conduction. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 27, 2017
    Publication date: July 5, 2018
    Inventors: Fay HUA, Hong XIE, Gregorio R. MURTAGIAN, Amit ABRAHAM, Alan C. MCALLISTER, Ting ZHONG
  • Publication number: 20180007791
    Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
    Type: Application
    Filed: September 12, 2017
    Publication date: January 4, 2018
    Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
  • Patent number: 9860988
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations to provide solder contacts for electrical connection in socket assemblies. In one embodiment, a solder contact may be disposed on the bottom surface of a die package such that the solder contact is conductively coupled to electrical contacts of the die package. The solder contacts may be disposed to be coupled to pins of a socket assembly, to provide conductive coupling of the electrical contacts of the die package and the pins of the socket assembly. The solder may be selected to be sufficiently soft to provide for better electrical conduction. The pins may also be configured to penetrate the solder contact to provide for better electrical conduction. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 20, 2014
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Fay Hua, Hong Xie, Gregorio R. Murtagian, Amit Abraham, Alan C. Mcallister, Ting Zhong
  • Patent number: 9832876
    Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
  • Patent number: 9692147
    Abstract: An electronic device connection system includes a first electrical device and a second electrical device. The first electrical device includes a plurality of electrical connectors disposed in, on, or about at least a portion of an exterior surface of the first electrical device. The second electrical device includes a plurality of electrical contacts disposed in, on, or about at least a portion of an exterior surface of the second electrical device. A mechanical compressor exerts a force on at least one of the first electrical device or the second electrical device such that the electrical connections on the first electrical device physically and conductively couple to the electrical contacts on the second electrical device. The device casing may function as the mechanical compressor. The electrical connectors and/or electrical contacts may include injection molded connectors that include a conductive material dispersed in a thermoplastic matrix.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 27, 2017
    Assignee: INTEL CORPORATION
    Inventors: Srikant Nekkanty, Donald T. Tran, Gregorio R. Murtagian