Abstract: A thermal control unit for controlling a patient's temperature includes a fluid outlet for delivering temperature-controlled fluid to a patient, a pump, a heat exchanger, a controller, and a user interface that displays a graph of patient temperature readings over time. The user interface also displays one or more event icons on the graph at locations corresponding to the time at which events associated with the event icons occurred. In some embodiments, the graph is displayed on a touch screen adapted to allow a user set maximum and minimum permissible temperatures for the fluid by touching areas of the graphs and/or by drawing on certain areas of the graph. An image of a human body having different zones may also be displayed on the user interface along with information pertaining to the thermal therapy being applied to the corresponding zones of the patient's body.

Abstract: A register file includes a substrate, a plurality of entries, and a plurality of read ports. Each entry includes a corresponding subset of a plurality of memory cells defined on the substrate. Each read port includes a plurality of access elements defined on the substrate. Each access element is associated with a particular common bit position of each of the entries. A plurality of entry access groups are disposed in adjacent columns on the substrate. Each entry access group is associated with a corresponding one of the plurality of entries and includes the access elements for all of the read ports for the corresponding entry.

Abstract: A register file includes a substrate, a plurality of entries, and a plurality of read ports. Each entry includes a corresponding subset of a plurality of memory cells defined on the substrate. Each read port includes a plurality of access elements defined on the substrate. Each access element is associated with a particular common bit position of each of the entries. A plurality of entry access groups are disposed in adjacent columns on the substrate. Each entry access group is associated with a corresponding one of the plurality of entries and includes the access elements for all of the read ports for the corresponding entry.

Abstract: An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan chain is further configured to capture data subsequent to applying the stimulus data. The integrated circuit also includes an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path. The embedded memory includes a virtual entry having a plurality of scan-controllable storage elements. During testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.

Abstract: An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan chain is further configured to capture data subsequent to applying the stimulus data. The integrated circuit also includes an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path. The embedded memory includes a virtual entry having a plurality of scan-controllable storage elements. During testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.

Abstract: A fuse cell circuit includes a first fuse and a first fuse sense circuit that senses a programming state of the first fuse and supplies an indication thereof. A sense control circuit includes a plurality of reference fuses and a second fuse sense circuit coupled to the reference fuses. The sense control circuit supplies a sense control signal to the fuse cell circuits to cause the fuse cell circuits to sense the programming state of the first fuse when the sense control signal is asserted. The sense control signal is asserted for a time period determined , at least in part, by a resistance value of the reference fuses. The integrated circuit may also include a resistance varying circuit coupled to vary a resistance value of a current path of the reference fuses according to one or more control signals.

Abstract: A clock generating circuit includes a clock generator and a cycle controller. The clock generator is coupled to receive a reference oscillating signal. The clock generator provides a clock signal responsive to the reference oscillating signal. The cycle controller is coupled to provide a cycle control signal to the clock generator. The clock generator stretches a cycle of the clock signal responsive to a first value of the cycle control signal.