Abstract: Process and apparatus for testing a microprocessor and dynamic RAM by a single tester where the microprocessor and dynamic RAM may be on a single card. The process makes the RAM appear static to an external static tester by separate read/write and refresh logic for the RAM. Two different clock generators connect to logic where each clock is selectively connectable to an on-board oscillator or to an external input. Priority logic for gating the refresh logic within a predetermined interval and gating the read/write logic at other times. The process includes three steps of a static logic test, a memory interface test, and, a functional test of the logic and the dynamic RAM. The third step is accomplished by executing a program in the on-card microprocessor. The three steps of the test form a single set of test data.