Patents by Inventor Gregory A. Gibbs

Gregory A. Gibbs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230359581
    Abstract: A system, and associated method, includes a plurality of data processing units, a target CPU, an interconnect unit that is separate from the target CPU and configured to receive a data payload and a prefix that includes a sequentially ordered list of the processing units that will perform the data operations and the sets of parameters to be used by each of the processing units, and based on the sequentially ordered list, the interconnect unit sends the data payload to a first processing unit, and receives back processed data, then sends the processed data to the subsequent processing unit, and receives back further processed data, and so forth until all of the data operations have been performed by the processing units set forth in the sequentially ordered list.
    Type: Application
    Filed: June 16, 2022
    Publication date: November 9, 2023
    Inventors: Sean Gregory GIBB, Saeed FOULADI FARD
  • Patent number: 11687365
    Abstract: A computational storage processor (CSP) is provided that includes the CSP comprising a plurality of submission queues (SQs), a plurality of computational storage functions (CSFs), a CSF controller, and a CSP controller, and a method of controlling the CSP is provided that includes directing a first submission queue entry (SQE) that is written to a first one of the plurality of SQs to the CSF controller, generating, by the CSF controller, one or more secondary SQEs based on the first SQE, each of the one or more secondary SQEs is directed to a respective one of the CSFs, writing, by the CSF controller, the one or more secondary SQEs to a second one of the plurality of SQs, directing each of the one or more secondary SQEs to an associated respective one of the CSFs, and for each of the one or more secondary SQEs, performing, by the associated respective one of the CSFs, an operation associated with the secondary SQE.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: June 27, 2023
    Assignee: EIDETIC COMMUNICATIONS INC.
    Inventors: Sean Gregory Gibb, Saeed Fouladi Fard
  • Publication number: 20220197704
    Abstract: A computational storage processor (CSP) is provided that includes the CSP comprising a plurality of submission queues (SQs), a plurality of computational storage functions (CSFs), a CSF controller, and a CSP controller, and a method of controlling the CSP is provided that includes directing a first submission queue entry (SQE) that is written to a first one of the plurality of SQs to the CSF controller, generating, by the CSF controller, one or more secondary SQEs based on the first SQE, each of the one or more secondary SQEs is directed to a respective one of the CSFs, writing, by the CSF controller, the one or more secondary SQEs to a second one of the plurality of SQs, directing each of the one or more secondary SQEs to an associated respective one of the CSFs, and for each of the one or more secondary SQEs, performing, by the associated respective one of the CSFs, an operation associated with the secondary SQE.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Inventors: Sean Gregory GIBB, Saeed FOULADI FARD
  • Patent number: 9170876
    Abstract: A method of decoding a primary codeword and a set of secondary codewords stored in a non-volatile memory (NVM), which includes reading, from the NVM, the primary codeword and all the secondary codewords and storing them in a second memory. The primary codeword is then read from the second memory and decoded, utilizing a soft-decision decoder, based on a log-likelihood ratio (LLR) vector. When the decoding of the primary codeword is unsuccessful: each secondary codeword of the set of secondary codewords is read from the second memory and decoded, utilizing a hard-decision decoder, to identify and correct errored data bits in the each secondary codeword and to determine a location of each errored data bit in the primary codeword. An adjusted LLR vector is generated by adjusting the LLR for each primary codeword data bit based on the determined locations of the errored data bits in the primary codeword.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: October 27, 2015
    Assignee: PMC-Sierra US, Inc.
    Inventors: Stephen Bates, Peter Graumann, Philip Lyon Northcott, Sean Gregory Gibb
  • Publication number: 20090229895
    Abstract: The invention provides an automobile vehicle pusher system, a hybrid or an electrical propulsion vehicle, and a method of reversibly converting a vehicle to hybrid or electrical propulsion. In a preferred aspect the invention provides such a system that can be reversibly connected to a trailer hitch or similar type device at the rear of a vehicle to provide propulsion in whole, or in part, for the vehicle. A further preferred embodiment includes connections and apparatus for charging of the electrical power storage components to provide a plug-in hybrid or plug-in electric only vehicle.
    Type: Application
    Filed: March 12, 2009
    Publication date: September 17, 2009
    Inventor: Gregory A. Gibbs