Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

Abstract: Designs and arrangements for sublimation cells are provided, which enriches an inert carrier gas with organic vapor such that the partial pressure of the organic vapor is highly stable in time. Stability is achieved by controlling the local rates of evaporation along the solid-gas interface through one or more crucibles, thereby reducing the effects of greater headspace and lowering interfacial area as the source depletes. Local evaporation rates also can be controlled using either temperature distribution or convective flow fields.

Abstract: A method and system for adhering roofing products to a supporting roof substrate, wherein ballast rock from a pre-existing roof insulation system is removed thereby exposing one or more layers of pre-existing insulation products supported by the roof substrate. In the case of new construction, the method contemplates installation of one or more layers of insulation products supported by the roof substrate. Core holes are formed through the one or more layers of insulation products thereby exposing the roof substrate. An anchor is attached to the roof substrate in each core hole void, and a binding agent is applied to each core hole void until the binding agent fills the core hole void, whereby the one or more layers of insulation products and roof substrate are locked together, preventing shifting of the insulation products without the need for adding ballast rocks thereon.

Abstract: A novel device and method of use featuring color-coded or otherwise distinguishable cannabis containing products wherein the color or distinguishable feature identifies the strain of cannabis contained in the item wherein users make their selection according to the type of strain desired and what type of effect it may have upon the user.

Abstract: Embodiments of systems and methods for combining downlink signals representative of a communication signal are provided herein. An example method comprises receiving samples of the downlink signals from multiple antenna feeds; generating first symbols for a first signal and second symbols for a second signal based on performing timing recovery operations on the first signal and the second signal, respectively; generating offset information based on performing a correlator operation on the first and second symbols; and combining the first and second signals based on performing a weighted combiner operation. At least one of the first timing recovery operation, the second timing recovery operation, the correlator operation, and the combing are performed in a plurality of processing blocks in one or more processors, wherein the first and second processing block operate in parallel.

Abstract: A sample injection device is provided with a syringe for injecting a sample and an arrangement unit in which plural kinds of cleaning solvents are arranged to clean the syringe. The device is configured to be able to set a cleaning order of the syringe by the plural kinds of cleaning solvents.

Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

Abstract: Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.

Abstract: Processing a digital bit stream and systems for implementing the methods are provided. The method includes dividing the digital bit stream into a plurality of data packets. In a first processing block performing a carrier recovery error calculation on a first portion of the plurality of data packets, comprising preforming a first phase locked loop (PLL) function on decimated data of the data packets and performing a carrier recovery operation on the first portion of the plurality of data packets. In a second processing block, in parallel with the processing of the first portion of the plurality of packets, performing the carrier recovery error calculation on a second portion of the plurality of data packets, comprising preforming the first PLL function on decimated data of the data packets and performing the carrier recovery operation on second portion of the plurality of data packets.

Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.

Abstract: Systems, apparatuses, and methods for thermal dissipation on or from an electronic device are described. An apparatus may have a printed circuit board (PCB) having an edge connector. At least one integrated circuit device may be disposed on a surface of the PCB. A tubular heat spreader may be disposed along an edge of the PCB opposite the edge connector.

Abstract: A method and system for adhering roofing products to a supporting roof substrate, wherein ballast rock from a pre-existing roof insulation system is removed thereby exposing one or more layers of pre-existing insulation products supported by the roof substrate. In the case of new construction, the method contemplates installation of one or more layers of insulation products supported by the roof substrate. Core holes are formed through the one or more layers of insulation products thereby exposing the roof substrate.

Abstract: Embodiments of systems and methods for combining downlink signals representative of a communication signal are provided herein. An example method comprises receiving the downlink signals from antenna feeds. In a first processing block(s) in a processor(s), performing a first blind detection operation on first packets of a first signal, and performing a first doppler compensation operation on the first packets. In a second processing block(s) in the processor(s) in parallel with the first processing block(s), performing a second blind detection operation on second packets of a second signal, and performing a second doppler compensation operation on the second packets. The method also comprises combining the first signal and the second signal based on (i) aligning the first data packets with the second data packets and (ii) performing a weighted combiner operation that applies scaling to the first and second packets based on corresponding signal quality.

Abstract: Embodiments of systems and methods for managing channel bandwidth of signals are provided herein. Example method include receiving signals from one or more antenna feeds, each signal having a first bandwidth. Some example methods include, in a plurality of processing blocks operating in parallel in one or more processors, performing one or more channelizer operations on portions of the signals, each channelizer operation creates a plurality of channels having a bandwidth smaller than the first bandwidth. Some methods may include, in a plurality of processing blocks in the one or more processors, performing one or more combiner operations on the channels, each operation combines the bandwidth of a subset of the channels into a combined channel, the plurality of processing blocks operating in parallel. The method then outputs the combined channel to a network.

Abstract: Embodiments of systems and methods for modulating a downlink signals representative of a communication signal are provided herein. An example method comprises receiving an input signal; in a first one or more processing blocks in a one or more processors, performing a first modulation operation on first data packets of the input signal based on a modulation scheme for a receiver of the downlink signal; in a second one or more processing blocks in the one or more processors in parallel with the first one or more processing blocks, performing a second modulation operation on second data packets of the input signal based on the modulation scheme; and generating a waveform as the downlink signal based on performing the first and second modulation operations.

Abstract: Embodiments of systems and methods for combining downlink signals representative of a communication signal are provided herein. An example method comprises receiving samples of the downlink signals from multiple antenna feeds; generating first symbols for a first signal and second symbols for a second signal based on performing timing recovery operations on the first signal and the second signal, respectively; generating offset information based on performing a correlator operation on the first and second symbols; and combining the first and second signals based on performing a weighted combiner operation. At least one of the first timing recovery operation, the second timing recovery operation, the correlator operation, and the combing are performed in a plurality of processing blocks in one or more processors, wherein the first and second processing block operate in parallel.

Abstract: Embodiments of systems and methods for simulating a downlink signal representative of a communication signal are provided herein. An example method comprises receiving an input signal; in a first one or more processing blocks in a one or more processors, performing a first operation to determine first one or more simulated effects representative of one or more effects that result from movement of a source of the downlink signal; in a second one or more processing blocks in the one or more processors in parallel with the first one or more processing blocks, performing a second operation to determine second one or more simulated effects representative of the one or more effects that result from movement of the source of the downlink signal; generating a simulated downlink signal by applying the first and second one or more simulated effects to the input signal; and outputting the simulated downlink signal.

Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.

Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

Abstract: At least one of method information representing an analysis execution method to be used for analysis of a sample and device information for specifying the configuration of an analysis device is acquired as analysis information by an analysis information acquirer. Syringe information for specifying the configuration of a syringe is acquired by a syringe information acquirer. Based on the analysis information and the syringe information, whether the syringe is suitable for analysis of the sample is judged by a judge. The result of judgement by the judge is presented by a presenter.