Abstract: Aspects of the disclosure provide for an apparatus. In an example, the apparatus includes a clock switching circuit coupled to oscillators and one or more circuit units. The clock switching circuit is configured to receive, from the oscillators, a set of frequency signals, provide an uplink primary clock signal and an enable signal to the one or more circuit units, the enable signal determined synchronously with the uplink primary clock signal, receive, from the one or more circuit units or a clock management circuit, a clock frequency request, provide the uplink primary clock signal based on a first signal of the set of frequency signals, and according to the clock frequency request, determining whether to continue to provide the uplink primary clock signal based on the first signal or on a second signal of the set of frequency signals.

Abstract: Disclosed examples include interface circuits to transfer data between a first register in a fast clock domain and a second register in a slow clock domain, including a resettable synchronizer to provide a synchronized start signal synchronized to a slow clock signal to initiate a write from the first register to the second register according to a write request signal, a pulse generator circuit to provide a write enable pulse signal according to the synchronized start signal, a write control circuit to selectively connect an output of the first register to an input of the second register to write data from the first register to the second register according to the write enable pulse signal, and a dual flip-flop to provide a reset signal synchronized to a fast clock signal according to the write request signal to clear any prior pending write request and begin a new write operation.

Abstract: Disclosed examples include interface circuits to transfer data between a first register in a fast clock domain and a second register in a slow clock domain, including a resettable synchronizer to provide a synchronized start signal synchronized to a slow clock signal to initiate a write from the first register to the second register according to a write request signal, a pulse generator circuit to provide a write enable pulse signal according to the synchronized start signal, a write control circuit to selectively connect an output of the first register to an input of the second register to write data from the first register to the second register according to the write enable pulse signal, and a dual flip-flop to provide a reset signal synchronized to a fast clock signal according to the write request signal to clear any prior pending write request and begin a new write operation.

Abstract: This invention is a method to extend data retention for FLASH based storage in a real time device embodied in generic semiconductor technology. This invention provides a manner to re-energize the Flash memory array to improve the retention characteristics of the memory without altering the clock cycle determinism of the system. Under certain conditions the Flash memory bit cells will lose their charge/non-charge over time. In this particular FLASH technology, an ECC is used to correct single bit errors within a 32 bit word. If there is time before multiple errors occur within a word, the single error cases are identified and “ReFlashed” to bring the value of the cell back to its “newly” programmed levels. This dramatically improves the long term retention characteristics of the memory while requiring some control logic and an area of non-volatile scratch/status information.

Abstract: This invention is a method to extend data retention for FLASH based storage in a real time device embodied in generic semiconductor technology. This invention provides a manner to re-energize the Flash memory array to improve the retention characteristics of the memory without altering the clock cycle determinism of the system. Under certain conditions the Flash memory bit cells will lose their charge/non-charge over time. In this particular FLASH technology, an ECC is used to correct single bit errors within a 32 bit word. If there is time before multiple errors occur within a word, the single error cases are identified and “ReFlashed” to bring the value of the cell back to its “newly” programmed levels. This dramatically improves the long term retention characteristics of the memory while requiring some control logic and an area of non-volatile scratch/status information.

Abstract: This disclosure describes a configuration data structure (100) that describes the functional characteristics of a single semiconductor device during the mass customization of semiconductor devices. The configuration data structure (100) includes a device identification member (110), a peripheral enable member (111), an alternate function select member (112), a port bonding specification member (113), and a resource specification member (114). In addition, this disclosure describes a system (300) that specifies and controls the functional characteristics of a single semiconductor device during the mass customization of semiconductor devices. The system (300) includes the following one or more internal peripheral buses (201), one or more peripherals (320-326), a functional I/O mux (302), a configuration data structure (100), and a GPIO (212).

Abstract: The present invention is a programmable Analog to Digital Converter (ADC) unit (200) that includes an analog to digital converter (204), which includes one or more analog inputs (202). The unit (200) additionally includes a control/status register block (216). The unit 200 further includes a FIFO register block (206) with a first, second, third, and fourth FIFO conversion register. Further included is a programmable sequencer (300) that includes a first (208), second (210), third (212), and fourth (214) programmable sample sequencer. And further, the unit (200) includes a first (226), second (228), third (230), and fourth (232) trigger event control multiplexer, where each trigger event control multiplexer corresponds to each programmable sample sequencer.

Abstract: The present invention is a programmable Analog to Digital Converter (ADC) unit (200) that includes an analog to digital converter (204), which includes one or more analog inputs (202). The unit (200) additionally includes a control/status register block (216). The unit 200 further includes a FIFO register block (20)6 with a first, second, third, and fourth FIFO conversion register. Further included is a programmable sequencer (300) that includes a first (208), second (210), third (212), and fourth (214) programmable sample sequencer And further, the unit (200) includes a first (226), second (228), third (230), and fourth (232) trigger event control multiplexer, where each trigger event control multiplexer corresponds to each programmable sample sequencer.