Patents by Inventor Gregory A. Overkamp
Gregory A. Overkamp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7472259Abstract: In one embodiment, a pipelined processor is described that includes an execution pipeline having a plurality of stages and a multi-cycle instruction (MCI) controller adapted to assert a stall signal to stall the multi-cycle instruction within one of the stages of the execution pipeline. The MCI controller is adapted to issue a plurality of instructions to subsequent stages in the pipeline while the multi-cycle instruction is stalled.Type: GrantFiled: December 6, 2000Date of Patent: December 30, 2008Assignee: Analog Devices, Inc.Inventors: Gregory A. Overkamp, Charles P. Roth, Ravi P. Singh
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Patent number: 7366876Abstract: In one embodiment, a state machine receives a plurality of instructions from an instruction register to be processed by a digital signal processor. After receiving a single RTI, the state machine loads each of the plurality of instructions one at time and determines the validity of each instruction. If the instruction is valid, the state machine transfers the instruction to the decoder. If the instruction is invalid or if a no-operation instruction is present, the state machine discards the instruction and immediately loads the next instruction.Type: GrantFiled: October 31, 2000Date of Patent: April 29, 2008Assignee: Analog Devices, Inc.Inventors: Charles P. Roth, Ravi P Singh, Gregory A. Overkamp, Tien Dinh
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Patent number: 7155570Abstract: In one embodiment, a trace buffer circuit for use with a pipelined digital signal processor (DSP) may include a series of interconnected registers that operate as a first-in first-out (FIFO) register on a write operation and a last-in first-out (LIFO) register on a read operation. On the write operation, a branch target/source address pair may be written to a first pair of trace buffer registers and, the contents of each register may be shifted two registers downstream. On the read operation, one instruction address may be read from a top register, and the contents of each register may be shifted one register upstream. The trace buffer may also include structure to enable compression of hardware and software loops in the program flow. A valid bit may be assigned to each instruction address in the trace buffer and a valid bit buffer with a structure parallel to that of the trace buffer may be provided to track the valid bits.Type: GrantFiled: September 29, 2000Date of Patent: December 26, 2006Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Ravi P. Singh, Charles P. Roth, Gregory A. Overkamp
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Patent number: 7069420Abstract: In one particular embodiment, a processor receives and processes a plurality of instruction from a single instruction register. The processor loads the plurality of instructions into a single register and determines the number and size of instructions while the instructions are in the register. Each of the plurality of instructions is then simultaneously presented to the decoder. The decoder then decodes a first of the plurality of instructions and determines whether any additional instructions are present.Type: GrantFiled: September 28, 2000Date of Patent: June 27, 2006Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Gregory A. Overkamp, Charles P. Roth, Ravi P. Singh
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Patent number: 7065636Abstract: In one embodiment, a programmable processor is adapted to support hardware loops. The processor may include hardware such as a first set of registers, a second set of registers, a first pipeline, and a second pipeline. Furthermore, the processor may include a control unit adapted to efficiently implement the hardware when performing a hardware loop.Type: GrantFiled: December 20, 2000Date of Patent: June 20, 2006Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Ryo Inoue, Ravi P. Singh, Charles P. Roth, Gregory A. Overkamp
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Patent number: 7036000Abstract: In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.Type: GrantFiled: May 17, 2004Date of Patent: April 25, 2006Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Charles P. Roth, Ravi P. Singh, Gregory A. Overkamp, Thomas Tomazin
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Patent number: 7028165Abstract: A programmable processor that includes a pipeline with a number of stages. A stall controller is associated with the pipeline, and detects a hazard condition in at least one of those stages. The stall controller produces a set of signals that can control the stages individually, to stall stages of the pipeline in order to avoid a hazard. In an embodiment, a bubble is formed in the pipeline which allows one instruction to complete prior to allowing the pipeline to continue.Type: GrantFiled: December 6, 2000Date of Patent: April 11, 2006Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Charles P. Roth, Ravi P. Singh, Gregory A. Overkamp
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Patent number: 6976151Abstract: In one embodiment, a processor receives coded instructions and converts the instructions to a second code prior to execution. The processor may be a digital signal processor. A decoder in the processor determines the destination of the instructions and performs decoding functions based on the destination.Type: GrantFiled: September 28, 2000Date of Patent: December 13, 2005Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Gregory A. Overkamp, Charles P. Roth, Ravi P. Singh
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Patent number: 6920547Abstract: Register adjustment is performed based on adjustment values determined at multiple stages within a pipeline of a processor. In one embodiment, a programmable processor is adapted to include a speculative count register. The speculative count register may be loaded with data associated with an instruction before the instruction commits. However, if the instruction is terminated before it commits, the speculative count register may be adjusted. A set of counters may monitor the difference between the speculative count register and its architectural counterpart.Type: GrantFiled: December 20, 2000Date of Patent: July 19, 2005Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Charles P. Roth, Ravi P. Singh, Gregory A. Overkamp
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Patent number: 6898693Abstract: In one embodiment, a programmable processor is adapted to include loop hardware to increase processing speed without significantly increasing power consumption. During a first pass through a loop, a first subset of a sequence of instructions may be loaded into the loop hardware. Then, during subsequent passes through the loop the first subset may be issued from the loop hardware while a second subset is retrieved from a memory device. In this manner, the second subset may be issued with no additional penalty after the first subset has been issued.Type: GrantFiled: November 2, 2000Date of Patent: May 24, 2005Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Ravi P. Singh, Charles P. Roth, Gregory A. Overkamp
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Patent number: 6889316Abstract: In an embodiment, a pipelined processor may be adapted to process multi-cycle instructions (MCIs). Results generated in response to non-terminal sub-instructions may be written to a speculative commit register. When the MCI commits, i.e., a terminal sub-instruction reaches the WB stage, the value in the speculative commit register may be written to the architectural register.Type: GrantFiled: March 28, 2001Date of Patent: May 3, 2005Assignees: Intel Corporation, Analog DevicesInventors: Ryo Inoue, Gregory A. Overkamp
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Patent number: 6842812Abstract: In one embodiment, a processor is arranged to handle events. The events handled by the processor have an assigned priority. When a first event is serviced, a first priority mask is generated based on the assigned priority of the first event. The priority mask indicates a set of serviceable events and a set of non-serviceable events and may be written to a priority register. When a second event is received, the priority mask is used to determine whether the second event should preempt the first event and be immediately serviced.Type: GrantFiled: November 2, 2000Date of Patent: January 11, 2005Assignee: Intel CorporationInventors: Charles P. Roth, Ravi P. Singh, Gregory A. Overkamp
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Patent number: 6829701Abstract: In one embodiment, a watchpoint engine generates watchpoints for code developed for a complex integrated circuit device such as a pipelined processor.Type: GrantFiled: December 15, 2000Date of Patent: December 7, 2004Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Charles P. Roth, Ravi P. Singh, Gregory A. Overkamp
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Patent number: 6823448Abstract: A programmable processor includes a execution pipeline and an exception pipeline. The execution pipeline may be a multi-stage execution pipeline that processes instructions. The exception pipeline may be a multi-stage exception pipeline that propagates exceptions resulting from the execution of the instructions. The execution and exception pipelines may have the same number of stages and may operate on the same clock cycles. When an instruction passes from a stage of the execution pipeline to a later stage of the execution pipeline, an exception may similarly pass from a corresponding stage of the exception pipeline to a corresponding later stage of the exception pipeline.Type: GrantFiled: December 15, 2000Date of Patent: November 23, 2004Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Charles P. Roth, Ravi P. Singh, Gregory A. Overkamp
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Publication number: 20040210744Abstract: In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.Type: ApplicationFiled: May 17, 2004Publication date: October 21, 2004Applicants: Intel Corporation, a Delaware corporation, Analog Devices, Inc., a Delaware corporationInventors: Charles P. Roth, Ravi P. Singh, Gregory A. Overkamp, Thomas Tomazin
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Patent number: 6789184Abstract: In an embodiment, an address pipeline corresponding to an instruction pipeline in a processor, for example, a digital signal processor (DSP), may generate and track the instruction address of each instruction at each stage. The address pipeline may include program count (PC) generation logic to automatically calculate the PC of the next instruction based on the width of the current instruction for sequential program flow. The address pipeline may also track valid bits associated with each instruction and store the address of the oldest valid instruction for return to the original program flow after a disruptive event.Type: GrantFiled: September 29, 2000Date of Patent: September 7, 2004Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Ravi P. Singh, Charles P. Roth, Gregory A. Overkamp
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Patent number: 6766444Abstract: In one embodiment, a programmable processor is arranged to include early registers to support hardware loops. In this manner, a system may increase processing speed without significantly increasing power consumption. Loop conditions of a loop may be loaded into a set of early registers. These conditions may then be detected from the early registers before the loop conditions are written to a set of architectural registers.Type: GrantFiled: November 2, 2000Date of Patent: July 20, 2004Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Ravi P. Singh, Charles P. Roth, Gregory A. Overkamp
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Patent number: 6754808Abstract: In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.Type: GrantFiled: September 29, 2000Date of Patent: June 22, 2004Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Charles P. Roth, Ravi P. Singh, Gregory A. Overkamp, Thomas Tomazin
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Patent number: 6748523Abstract: In one embodiment, a programmable processor is configured to support a loop setup instruction. The loop setup instruction may be decoded and a zero offset loop may be detected from the loop setup instruction. The next instruction in the instruction stream may then be immediately issued as a first instruction in a loop. The loop setup instruction may also be used to detect a single instruction loop.Type: GrantFiled: November 2, 2000Date of Patent: June 8, 2004Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Ravi P. Singh, Charles P. Roth, Gregory A. Overkamp
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Patent number: 6728870Abstract: In one embodiment, a programmable processor is adapted to conditionally move data between a pointer register and a data register in response to a single machine instruction. The processor has a plurality of pipelines. In response to the machine instruction, a control unit directs the pipelines to forward the data across the pipelines in order to move the data between the registers.Type: GrantFiled: October 6, 2000Date of Patent: April 27, 2004Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Charles P. Roth, Ravi P. Singh, Gregory A. Overkamp, Ryo Inoue