Abstract: An integrated interface integrates a bus repeater and remote terminal into a single interface linking a main bus and an extended bus in a communication system. In one embodiment, the remote terminal communicates directly with the bus repeater to monitor bus repeater operation. By integrating the bus repeater and remote terminal together, the integrated interface can use only one set of input and output components for both the bus repeater and remote terminal, reducing the total number of components in the communication system.

Abstract: A divider unit (15), having a divider circuit (16) and a divider controller (17), generates signed quotient and signed remainder signals in response to input signed dividend and signed divisor signals. The divider circuit (16) has an adder/subtracter unit (22), a mux (24), a zero/sign detector unit (23), and a shiftable register (28) which are controlled by the divider controller (17) and which cooperate to iteratively generate signed partial remainder and signed partial dividend signals, necessary for the computation of signed quotient and signed remainder signals, using either a restoring or non-restoring binary division algorithm.

Abstract: A reduced instruction set computer (RISC) with a Harvard architecture is disclosed. The RISC may be designed to be used simply as a RISC or may be designed to be used to emulate a complex instruction set computer (CISC). Or, it may be designed for use as either. A CISC design methodology is disclosed whereby a RISC is designed and fabricated and whereby RISC emulation code is written concurrently with design and fabrication and also subsequent to fabrication.

Abstract: A data hub for facilitating and effecting data transfers between signal processors with high efficiency is disclosed. The data hub receives low priority data transfer instructions from a master CPU and is capable of transferring such low priority data between processors without imposing significant overhead burdens on either the data source or destination. The hub may have the further capability of asynchronously receiving intermediate priority data transfers, storing the received data and transferring it to a destination unit before any further low priority transfers are effected. The hub may have the further capability of asynchronously receiving high priority transfer requests which are effected by the hub before both intermediate and low priority transfers. The hub may be used as a keystone building block for use in linking signal processors.