Abstract: A quantum dot structure having a split-gate geometry is provided. The quantum dot is configured for incorporation into a quantum dot array of a quantum processing unit. A gap between a reservoir accumulation gate and a quantum dot accumulation gate provides a tunnel barrier between an electric charge reservoir and a quantum dot well. An electrical potential applied to the gates defines a tunnel barrier height, width and charge tunneling rate between the well and the reservoir without relying on any barrier gate to control the charge tunneling rate.

Abstract: A quantum dot structure having a split-gate geometry is provided. The quantum dot is configured for incorporation into a quantum dot array of a quantum processing unit. A gap between a reservoir accumulation gate and a quantum dot accumulation gate provides a tunnel barrier between an electric charge reservoir and a quantum dot well. An electrical potential applied to the gates defines a tunnel barrier height, width and charge tunneling rate between the well and the reservoir without relying on any barrier gate to control the charge tunneling rate.

Abstract: The fabrication of small-scale structures is disclosed. A unit-cell of a small-scale structure with non-planar features is fabricated by forming a membrane on a suitable material. A pattern is formed in the membrane and a portion of the substrate underneath the membrane is removed to form a cavity. Resonators are then directionally deposited on the wall or sides of the cavity. The cavity may be rotated during deposition to form closed-loop resonators. The resonators may be non-planar. The unit-cells can be formed in a layer that includes an array of unit-cells.

Abstract: The fabrication of small-scale structures is disclosed. A unit-cell of a small-scale structure with non-planar features is fabricated by forming a membrane on a suitable material. A pattern is formed in the membrane and a portion of the substrate underneath the membrane is removed to form a cavity. Resonators are then directionally deposited on the wall or sides of the cavity. The cavity may be rotated during deposition to form closed-loop resonators. The resonators may be non-planar. The unit-cells can be formed in a layer that includes an array of unit-cells.

Abstract: A fiber array is provided for use in optical systems requiring a one-dimensional or two-dimensional array of fibers. The fiber array includes a support post disposed within a fiber-containing cavity of the fiber array to provide support within the internal cavity. The use of the support post permits the height of the fiber array to be reduced thereby enabling such fiber arrays to be stacked together more closely providing increased fiber packing density among arrays. In addition, the fiber array is configured to support and protect un-jacketed fibers, where the absence of the jacket permits increased packing density among fibers in an individual fiber array.

Abstract: Methods for making a micromachined device (e.g. an microoptical submount) having positive features (extending up from a device surface) and negative features (extending into the device surface). The present techniques locate the postive feature and negative features according to a single mask step. In one embodiment, a hard mask is patterned on top of the device layer of an SOI wafer. Then, RIE is used to vertically etch to the etch stop layer, forming the positive feature. Then, the positive feature is masked, and metal or hard mask is deposited on the exposed areas of the etch stop layer. Then, portions of the device layer are removed, leaving the patterned metal layer on the etch stop layer. Then, the etch stop layer is removed in an exposed area, uncovering the handle layer. Then, the handle layer is etched in an exposed area to form the negative feature.

Abstract: A fiber array is provided for use in optical systems requiring a one-dimensional or two-dimensional array of fibers. The fiber array includes a support post disposed within a fiber-containing cavity of the fiber array to provide support within the internal cavity. The use of the support post permits the height of the fiber array to be reduced thereby enabling such fiber arrays to be stacked together more closely providing increased fiber packing density among arrays. In addition, the fiber array is configured to support and protect un-jacketed fibers, where the absence of the jacket permits increased packing density among fibers in an individual fiber array.

Abstract: Methods for making a micromachined device (e.g. an microoptical submount) having positive features (extending up from a device surface) and negative features (extending into the device surface). The present techniques locate the positive feature and negative features according to a single mask step. In one embodiment, a hard mask is patterned on top of the device layer of an SOI wafer. Then, RIE is used to vertically etch to the etch stop layer, forming the positive feature. Then, the positive feature is masked, and metal or hard mask is deposited on the exposed areas of the etch stop layer. Then, portions of the device layer are removed, leaving the patterned metal layer on the etch stop layer. Then, the etch stop layer is removed in an exposed area, uncovering the handle layer. Then, the handle layer is etched in an exposed area to form the negative feature.