Abstract: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of word lines (e.g., first and second word lines) and a plurality of word line segments (e.g., first and second word line segments) wherein each word line segment is coupled to an associated word line (e.g., a first segment is associated with the first word line and a second segment is associated with the second word line). The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, wherein the body region is electrically floating, and a gate coupled to an associated word line via an associated word line segment.

Abstract: There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, circuitry and techniques for reading, writing and/or operating semiconductor memory cells of a memory cell array, including, for example, electrically floating body transistors in which an electrical charge is stored in the body of the transistor. In one aspect, the present inventions are directed to one or more independently controllable parameters of a memory operation (e.g., restore, write, refresh), to program or write a data state into a memory cell. In one embodiment, the parameter is the amount of time of programming or writing a predetermined data state into a memory cell. In another embodiment, the controllable parameter is the amplitude of the voltage of the control signals applied to the gate, drain region and/or source region during programming or writing a predetermined data state into a memory cell. Indeed, the controllable parameters may be both temporal and voltage amplitude.

Abstract: There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, circuitry and techniques for reading, writing and/or operating semiconductor memory cells of a memory cell array, including, for example, electrically floating body transistors in which an electrical charge is stored in the body of the transistor. In one aspect, the present inventions are directed to one or more independently controllable parameters of a memory operation (e.g., restore, write, refresh), to program or write a data state into a memory cell. In one embodiment, the parameter is the amount of time of programming or writing a predetermined data state into a memory cell. In another embodiment, the controllable parameter is the amplitude of the voltage of the control signals applied to the gate, drain region and/or source region during programming or writing a predetermined data state into a memory cell. Indeed, the controllable parameters may be both temporal and voltage amplitude.

Abstract: There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, circuitry and techniques for reading, writing and/or operating a semiconductor memory cells of a memory cell array, including electrically floating body transistors in which an electrical charge is stored in the body of the transistor. In one aspect, the present inventions are directed to one or more independently controllable parameters of a memory operation (for example, restore, write, refresh), to program or write a data state into a memory cell. In one embodiment, the parameter is the amount of time of programming or writing a predetermined data state into a memory cell. In another embodiment, the controllable parameter is the amplitude of the voltage of the control signals applied to the gate, drain region and/or source region during programming or writing a predetermined data state into a memory cell. Indeed, the controllable parameters may be both temporal and voltage amplitude.

Abstract: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of word lines (e.g., first and second word lines) and a plurality of word line segments (e.g., first and second word line segments) wherein each word line segment is coupled to an associated word line (e.g., a first segment is associated with the first word line and a second segment is associated with the second word line). The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, wherein the body region is electrically floating, and a gate coupled to an associated word line via an associated word line segment.