Patents by Inventor Gregory Ameriada Uvieghara
Gregory Ameriada Uvieghara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9318165Abstract: A sense amplifier is disclosed that includes an amplifier circuit configured to receive, at an input, an input signal including an input level, the amplifier circuit configured to provide an amplified output signal including a gain with respect to the input level; and a feedback circuit coupled to receive the amplified output signal from the amplifier circuit, the feedback circuit configured to provide, at the input of the amplifier circuit, an adjusted version of the amplified output signal including a modified output magnitude based on common mode feedback.Type: GrantFiled: March 18, 2014Date of Patent: April 19, 2016Assignee: QUALCOMM IncorporatedInventors: Chulmin Jung, Rui Li, Sei Seung Yoon, Gregory Ameriada Uvieghara
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Patent number: 9252765Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.Type: GrantFiled: August 29, 2014Date of Patent: February 2, 2016Assignee: QUALCOMM IncorporatedInventors: Esin Terzioglu, Gregory Ameriada Uvieghara, Sei Seung Yoon, Balachander Ganesan, Anil Chowdary Kota
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Publication number: 20150269978Abstract: A sense amplifier is disclosed that includes an amplifier circuit configured to receive, at an input, an input signal including an input level, the amplifier circuit configured to provide an amplified output signal including a gain with respect to the input level; and a feedback circuit coupled to receive the amplified output signal from the amplifier circuit, the feedback circuit configured to provide, at the input of the amplifier circuit, an adjusted version of the amplified output signal including a modified output magnitude based on common mode feedback.Type: ApplicationFiled: March 18, 2014Publication date: September 24, 2015Applicant: QUALCOMM IncorporatedInventors: Chulmin Jung, Rui Li, Sei Seung Yoon, Gregory Ameriada Uvieghara
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Publication number: 20150242213Abstract: Various embodiments of methods and systems for flexible read only memory (“ROM”) storage of coded instructions in a portable computing device (“PCD”) are disclosed. Because certain instructions and/or data associated with a primary boot loader (“PBL”) may be defective or in need of modification after manufacture of a mask ROM component, embodiments of flexible ROM storage (“FRS”) systems and methods use a closely coupled one-time programmable (“OTP”) memory component to store modified instructions and/or data. Advantageously, because the OTP memory component may be manufactured “blank” and programmed at a later time, modifications to code and/or data stored in an unchangeable mask ROM may be accomplished via pointers in fuses of a security controller that branch the request to the OTP and bypass the mask ROM.Type: ApplicationFiled: February 23, 2014Publication date: August 27, 2015Applicant: QUALCOMM INCORPORATEDInventors: YANRU LI, DEXTER TAMIO CHUN, DHAMIM PACKER ALI, GREGORY AMERIADA UVIEGHARA, ZHONGZE WANG
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Patent number: 9082498Abstract: A thin gate-oxide dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit is configured to bias the switched n-well to prevent voltage damage to the dual-mode PMOS transistor without the use of native transistors.Type: GrantFiled: August 8, 2013Date of Patent: July 14, 2015Assignee: QUALCOMM IncorporatedInventors: Gregory Ameriada Uvieghara, Sei Seung Yoon
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Publication number: 20150043265Abstract: A thin gate-oxide dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit is configured to bias the switched n-well to prevent voltage damage to the dual-mode PMOS transistor without the use of native transistors.Type: ApplicationFiled: August 8, 2013Publication date: February 12, 2015Applicant: QUALCOMM IncorporatedInventors: Gregory Ameriada Uvieghara, Sei Seung Yoon
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Publication number: 20140369152Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.Type: ApplicationFiled: August 29, 2014Publication date: December 18, 2014Inventors: Esin Terzioglu, Gregory Ameriada Uvieghara, Sei Seung Yoon, Balachander Ganesan, Anil Chowdary Kota
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Patent number: 8908464Abstract: Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (NVM), test cells associated with the NVM are read first. The test cells share a common power supply with the NVM and output read values from the test cells are configured to deviate from values pre-programmed in the test cells when a subnormal read voltage is applied on the common power supply. Thus, by comparing the output read values with the pre-programmed values, it can be determined whether voltage of the common power supply is subnormal, wherein configuration information will be read incorrectly at a subnormal read voltage. If the voltage is subnormal, power up is aborted. Otherwise, power up is allowed to proceed by reading the configuration information from the NVM.Type: GrantFiled: February 12, 2013Date of Patent: December 9, 2014Assignee: QUALCOMM IncorporatedInventors: Gregory Ameriada Uvieghara, Michael Batenburg, Esin Terzioglu, Yucong Tao
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Patent number: 8830779Abstract: A fuse-based memory includes a plurality of bit lines. Each bit lines couples to a corresponding plurality of fuses. The fuses couple to ground through corresponding access transistors. The memory is configured to precharge an accessed one of the bit lines and a reference one of the bit lines using a low voltage supply. In contrast, a resulting voltage difference between the accessed bit line and the reference bit line is sensed using a sense amplifier powered by a high voltage supply, wherein a high voltage supplied by the high power supply is greater than a low voltage supplied by the low voltage supply.Type: GrantFiled: June 24, 2013Date of Patent: September 9, 2014Assignee: QUALCOMM IncorporatedInventors: Esin Terzioglu, Gregory Ameriada Uvieghara, Sei Seung Yoon, Balachander Ganesan, Anil Chowdary Kota
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Publication number: 20140226426Abstract: Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (NVM), test cells associated with the NVM are read first. The test cells share a common power supply with the NVM and output read values from the test cells are configured to deviate from values pre-programmed in the test cells when a subnormal read voltage is applied on the common power supply. Thus, by comparing the output read values with the pre-programmed values, it can be determined whether voltage of the common power supply is subnormal, wherein configuration information will be read incorrectly at a subnormal read voltage. If the voltage is subnormal, power up is aborted. Otherwise, power up is allowed to proceed by reading the configuration information from the NVM.Type: ApplicationFiled: February 12, 2013Publication date: August 14, 2014Applicant: QUALCOMM IncorporatedInventors: Gregory Ameriada Uvieghara, Michael Batenburg, Esin Terzioglu, Yucong Tao
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Patent number: 8787096Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.Type: GrantFiled: January 16, 2013Date of Patent: July 22, 2014Assignee: QUALCOMM IncorporatedInventors: Esin Terzioglu, Gregory Ameriada Uvieghara, Sei Seung Yoon, Balachander Ganesan, Anil Chowdary Kota
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Publication number: 20140198588Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.Type: ApplicationFiled: January 16, 2013Publication date: July 17, 2014Applicant: QUALCOMM IncorporatedInventors: Esin Terzioglu, Gregory Ameriada Uvieghara, Sei Seung Yoon, Balachander Ganesan, Anil Chowdary Kota