Abstract: An apparatus comprises processing circuitry to issue demand memory access requests to access data stored in a memory system. Stride pattern detection circuitry detects whether a sequence of demand target addresses specified by the demand memory access requests includes two or more constant stride sequences of addresses interleaved within the sequence of demand target addresses. Each constant stride sequence comprises addresses separated by intervals of a constant stride value. Prefetch control circuitry controls issuing of prefetch load requests to prefetch data from the memory system. The prefetch load requests specify prefetch target addresses predicted based on the constant stride sequences detected by the stride pattern detection circuitry.

Abstract: An apparatus comprises processing circuitry to issue demand memory access requests to access data stored in a memory system. Stride pattern detection circuitry detects whether a sequence of demand target addresses specified by the demand memory access requests includes two or more constant stride sequences of addresses interleaved within the sequence of demand target addresses. Each constant stride sequence comprises addresses separated by intervals of a constant stride value. Prefetch control circuitry controls issuing of prefetch load requests to prefetch data from the memory system. The prefetch load requests specify prefetch target addresses predicted based on the constant stride sequences detected by the stride pattern detection circuitry.

Abstract: An apparatus and method are provided for handling atomic update operations. The apparatus has a cache storage to store data for access by processing circuitry, the cache storage having a plurality of cache lines. Atomic update handling circuitry is used to handle performance of an atomic update operation in respect of data at a specified address. When data at the specified address is determined to be stored within a cache line of the cache storage, the atomic update handling circuitry performs the atomic update operation on the data from that cache line. Hazard detection circuitry is used to trigger deferral of performance of the atomic update operation upon detecting that a linefill operation for the cache storage is pending that will cause a chosen cache line to be populated with data that includes data at the specified address. The linefill operation causes the apparatus to receive a sequence of data portions that collectively form the data for storing in the chosen cache line.

Abstract: An apparatus and method are provided for handling atomic update operations. The apparatus has a cache storage to store data for access by processing circuitry, the cache storage having a plurality of cache lines. Atomic update handling circuitry is used to handle performance of an atomic update operation in respect of data at a specified address. When data at the specified address is determined to be stored within a cache line of the cache storage, the atomic update handling circuitry performs the atomic update operation on the data from that cache line. Hazard detection circuitry is used to trigger deferral of performance of the atomic update operation upon detecting that a linefill operation for the cache storage is pending that will cause a chosen cache line to be populated with data that includes data at the specified address. The linefill operation causes the apparatus to receive a sequence of data portions that collectively form the data for storing in the chosen cache line.