Patents by Inventor Gregory B. Zyner

Gregory B. Zyner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Floating point multiplier with reduced critical paths using delay matching techniques
    Patent number: 5790446
    Abstract: A floating point multiplier with partial support for subnormal operands and results uses radix-4 or modified Booth encoding and a binary tree of 4:2 compressors to generate the 53.times.53 double-precision product. Delay matching techniques in the binary tree stage and in the final addition stage reduce cycle time. Improved rounding and sticky-bit generating techniques further reduce area and timing. The overall multiplier has a latency of 3 cycles, a throughput of 1 cycle, and a cycle time of 6.0 ns.
    Type: Grant
    Filed: July 5, 1995
    Date of Patent: August 4, 1998
    Assignee: Sun Microsystems, Inc.
    Inventors: Robert K. Yu, Gregory B. Zyner