Patents by Inventor Gregory Bakker

Gregory Bakker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flash/dynamic random access memory field programmable gate array
    Publication number: 20050190626
    Abstract: A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.
    Type: Application
    Filed: April 21, 2005
    Publication date: September 1, 2005
    Inventors: John McCollum, Vidya Bellippady, Gregory Bakker
  • Flash/dynamic random access memory field programmable gate array
    Patent number: 6891769
    Abstract: A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: May 10, 2005
    Assignee: Actel Corporation
    Inventors: John McCollum, Vidya Bellippady, Gregory Bakker
  • Flash/dynamic random access memory field programmable gate array
    Publication number: 20050013186
    Abstract: A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.
    Type: Application
    Filed: July 17, 2003
    Publication date: January 20, 2005
    Inventors: John McCollum, Vidya Bellippady, Gregory Bakker