Patents by Inventor Gregory Bidal
Gregory Bidal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9941416Abstract: A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions. In the channel region, the semiconductor layer is formed from a portion of an upper semiconductor layer of a silicon on insulator substrate. In the source and drain regions, the semiconductor layer is formed by epitaxially grown semiconductor material.Type: GrantFiled: November 18, 2016Date of Patent: April 10, 2018Assignee: STMicroelectronics (Crolles 2) SASInventor: Gregory Bidal
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Patent number: 9876032Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.Type: GrantFiled: October 18, 2016Date of Patent: January 23, 2018Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Sonarith Chhun, Emmanuel Josse, Gregory Bidal, Dominique Golanski, Francois Andrieu, Jerome Mazurier, Olivier Weber
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Publication number: 20170317106Abstract: An integrated circuit is formed using a substrate of a silicon-on-insulator type that includes a carrier substrate and a stack of a buried insulating layer and a semiconductor film on the carrier substrate. A first region without the stack separates a second region that includes the stack from a third region that also includes the stack. An MOS transistor has a gate dielectric region formed by a portion of the buried insulating layer in the second region and a gate region formed by a portion of the semiconductor film in the second region. The carrier substrate incorporates doped regions under the first region which form at least a part of a source region and drain region of the MOS transistor.Type: ApplicationFiled: November 28, 2016Publication date: November 2, 2017Applicants: STMicroelectronics (Rousset 2) SAS, STMicroelectronics (Crolles 2) SASInventors: Philippe Boivin, Franck Arnaud, Gregory Bidal, Dominique Golanski, Emmanuel Richard
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Patent number: 9786755Abstract: An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate. In the second zone, the semiconductor film has been removed. The second transistor in the second zone includes a gate-dielectric region resting on the carrier substrate that is formed by a portion of the buried insulating layer). The first transistor in the first zone includes a gate-dielectric region formed by a dielectric layer on the semiconductor film.Type: GrantFiled: November 2, 2015Date of Patent: October 10, 2017Assignee: STMicroelectronics (Crolles 2) SASInventors: Dominique Golanski, Gregory Bidal, Simon Jeannot
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Publication number: 20170117296Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.Type: ApplicationFiled: October 18, 2016Publication date: April 27, 2017Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Sonarith Chhun, Emmanuel Josse, Gregory Bidal, Dominique Golanski, Francois Andrieu, Jerome Mazurier, Olivier Weber
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Publication number: 20170069764Abstract: A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions. In the channel region, the semiconductor layer is formed from a portion of an upper semiconductor layer of a silicon on insulator substrate. In the source and drain regions, the semiconductor layer is formed by epitaxially grown semiconductor material.Type: ApplicationFiled: November 18, 2016Publication date: March 9, 2017Applicant: STMicroelectronics (Crolles 2) SASInventor: Gregory Bidal
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Patent number: 9530686Abstract: A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions. In the channel region, the semiconductor layer is formed from a portion of an upper semiconductor layer of a silicon on insulator substrate. In the source and drain regions, the semiconductor layer is formed by epitaxially grown semiconductor material.Type: GrantFiled: February 15, 2016Date of Patent: December 27, 2016Assignee: STMicroelectronics (Crolles 2) SASInventor: Gregory Bidal
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Publication number: 20160284807Abstract: A substrate of the silicon-on-insulator type is formed from an initial substrate of the silicon-on-insulator type having a semiconductor film on top of a buried insulating layer itself situated on top of a carrier substrate. A localized modification of a thickness of the semiconductor film is made so as to form a semiconductor film having different thicknesses in different regions.Type: ApplicationFiled: November 2, 2015Publication date: September 29, 2016Applicants: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS SAInventors: David Petit, Frederic Monsieur, Xavier Federspiel, Gregory Bidal
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Publication number: 20160276451Abstract: An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate. In the second zone, the semiconductor film has been removed. The second transistor in the second zone includes a gate-dielectric region resting on the carrier substrate that is formed by a portion of the buried insulating layer). The first transistor in the first zone includes a gate-dielectric region formed by a dielectric layer on the semiconductor film.Type: ApplicationFiled: November 2, 2015Publication date: September 22, 2016Applicant: STMicroelectronics (Crolles 2) SASInventors: Dominique Golanski, Gregory Bidal, Simon Jeannot
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Patent number: 9117876Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.Type: GrantFiled: July 31, 2014Date of Patent: August 25, 2015Assignee: STMicroelectronics (Crolles 2) SASInventors: Grégory Bidal, Laurent Favennec, Raul Andres Bianchi
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Patent number: 8912067Abstract: A method for manufacturing three types of MOS transistors in three regions of a same substrate, including the steps of: forming a first insulating layer, removing the first insulating layer from the first and second regions, forming a silicon oxide layer, depositing an insulating layer having a dielectric constant which is at least twice greater than that of silicon oxide, depositing a first conductive oxygen scavenging layer, removing the first conductive layer from the second and third regions, and annealing.Type: GrantFiled: September 20, 2011Date of Patent: December 16, 2014Assignee: STMicroelectronics (Crolles 2) SASInventors: Jean-Luc Huguenin, Grégory Bidal
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Publication number: 20140342524Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.Type: ApplicationFiled: July 31, 2014Publication date: November 20, 2014Applicant: STMicroelectronics (Crolles 2) SASInventors: Grégory Bidal, Laurent Favennec, Raul Andres Bianchi
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Patent number: 8829622Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.Type: GrantFiled: June 13, 2012Date of Patent: September 9, 2014Assignee: STMicroelectronics (Crolles 2) SASInventors: Grégory Bidal, Laurent Favennec, Raul Andres Bianchi
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Publication number: 20120319206Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.Type: ApplicationFiled: June 13, 2012Publication date: December 20, 2012Applicant: STMicroelectronics (Crolles 2) SASInventors: Grégory Bidal, Laurent Favennec, Raul Andres Bianchi
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Patent number: 8288754Abstract: The present invention relates to a method for position-controlled fabrication of a semiconductor quantum dot, the method comprising: providing a substrate (102) of a substrate material; depositing a sacrificial layer (108) of a sacrificial material; depositing an active layer (110) of a semiconductive active material on the sacrificial layer, wherein the substrate, sacrificial and active materials are chosen such that the sacrificial layer is selectively removable with respect to the substrate and the active layer, depositing and patterning a mask layer on the active layer so as to define desired quantum-dot positions in lateral directions, fabricating a lateral access to the sacrificial layer in regions underneath the patterned mask layer; selectively removing, with respect to the substrate and the active layer, the sacrificial layer from underneath the active layer at least under the patterned mask layer; and etching the active layer under the patterned mask layer from underneath the active layer so as to aType: GrantFiled: March 11, 2009Date of Patent: October 16, 2012Assignees: NXP B.V., ST MicroElectronics (Crolles 2) SASInventors: Gregory Bidal, Frederic Boeuf, Nicolas Loubet
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Publication number: 20120083110Abstract: A method for manufacturing three types of MOS transistors in three regions of a same substrate, including the steps of: forming a first insulating layer, removing the first insulating layer from the first and second regions, forming a silicon oxide layer, depositing an insulating layer having a dielectric constant which is at least twice greater than that of silicon oxide, depositing a first conductive oxygen scavenging layer, removing the first conductive layer from the second and third regions, and annealing.Type: ApplicationFiled: September 20, 2011Publication date: April 5, 2012Applicant: STMicroelectronics (Crolles 2) SASInventors: Jean-Luc Huguenin, Grégory Bidal
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Publication number: 20110006280Abstract: The present invention relates to a method for position-controlled fabrication of a semiconductor quantum dot, the method comprising: providing a substrate (102) of a substrate material; depositing a sacrificial layer (108) of a sacrificial material; depositing an active layer (110) of a semiconductive active material on the sacrificial layer, wherein the substrate, sacrificial and active materials are chosen such that the sacrificial layer is selectively removable with respect to the substrate and the active layer, depositing and patterning a mask layer on the active layer so as to define desired quantum-dot positions in lateral directions, fabricating a lateral access to the sacrificial layer in regions underneath the patterned mask layer; selectively removing, with respect to the substrate and the active layer, the sacrificial layer from underneath the active layer at least under the patterned mask layer; and etching the active layer under the patterned mask layer from underneath the active layer so as to aType: ApplicationFiled: March 11, 2009Publication date: January 13, 2011Inventors: Gregory Bidal, Frederic Boeuf, Nicolas Loubet
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Publication number: 20100102402Abstract: A method of forming a field effect transistor comprising a gate formed on an insulating layer, the gate having, in a zone in contact with the insulating layer, a semiconducting central zone and lateral zones in the length of the gate, the method comprising forming a gate comprising a portion of insulating layer, a portion of semiconducting layer formed over the insulating layer, and a portion of mask layer formed over the semiconducting layer; performing an etching of the portion of the mask layer such that only a portion in the centre of the gate remains; and reacting the semiconducting gate with a metal deposited over the gate.Type: ApplicationFiled: January 10, 2008Publication date: April 29, 2010Applicants: STMicroelectronics (Crolles) 2 SAS, NXP B.V. (Dutch Corporation)Inventors: Markus Müller, Grégory Bidal