Patents by Inventor Gregory C. Baldwin

Gregory C. Baldwin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Marker layer to facilitate mask build with interactive layers
    Patent number: 8595656
    Abstract: A mask build system includes a program for configuring mask layers and a fabrication site for compiling configured mask layers. The system includes at least one database configured by a system processor, the database comprising drawn layers for fabricating reticles of a semiconductor device; and a marker layer configured to define layer dependent features, the marker layer handed off with that part of the at least one database which will support subsequent layers of the database without altering flow of mask build at the fabrication site.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: November 26, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas J. Aton, Gregory C. Baldwin, Robert L. Pitts
  • MARKER LAYER TO FACILITATE MASK BUILD WITH INTERACTIVE LAYERS
    Publication number: 20120102441
    Abstract: A mask build system includes a program for configuring mask layers and a fabrication site for compiling configured mask layers. The system includes at least one database configured by a system processor, the database comprising drawn layers for fabricating reticles of a semiconductor device; and a marker layer configured to define layer dependent features, the marker layer handed off with that part of the at least one database which will support subsequent layers of the database without altering flow of mask build at the fabrication site.
    Type: Application
    Filed: October 21, 2010
    Publication date: April 26, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Thomas J. Aton, Gregory C. Baldwin, Robert L. Pitts
  • On-chip ESD protection in dual voltage CMOS
    Patent number: 6143594
    Abstract: In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.
    Type: Grant
    Filed: January 26, 2000
    Date of Patent: November 7, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Alwin J. Tsao, Vikas I. Gupta, Gregory C. Baldwin, E. Ajith Amerasekera, David B. Spratt, Timothy A. Rost
  • On-chip ESD protection in dual voltage CMOS
    Patent number: 6137144
    Abstract: In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: October 24, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Alwin J. Tsao, Vikas I. Gupta, Gregory C. Baldwin, E. Ajith Amerasekera, David B. Spratt, Timothy A. Rost