Patents by Inventor Gregory C. Eiden

Gregory C. Eiden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6259091
    Abstract: An apparatus for producing an ion beam having an increased proportion of analyte ions compared to carrier gas ions is disclosed. Specifically, the apparatus has an ion trap or a collision cell containing a reagent gas wherein the reagent gas accepts charge from the analyte ions thereby selectively neutralizing the carrier gas ions. Also disclosed is the collision cell as employed in various locations within analytical instruments including an inductively coupled plasma mass spectrometer.
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: July 10, 2001
    Assignee: Battelle Memorial Institute
    Inventors: Gregory C. Eiden, Charles J. Barinaga, David W. Koppenaal
  • Patent number: 5767512
    Abstract: A method for producing an ion beam having an increased proportion of analyte ions compared to carrier gas ions is disclosed. Specifically, the method has the step of addition of a charge transfer gas to the carrier analyte combination that accepts charge from the carrier gas ions yet minimally accepts charge from the analyte ions thereby selectively neutralizing the carrier gas ions. Also disclosed is the method as employed in various analytical instruments including an inductively coupled plasma mass spectrometer.
    Type: Grant
    Filed: January 5, 1996
    Date of Patent: June 16, 1998
    Assignee: Battelle Memorial Institute
    Inventors: Gregory C. Eiden, Charles J. Barinaga, David W. Koppenaal
  • Patent number: 4902640
    Abstract: A mixed bipolar-CMOS self-aligned process and integrated circuit provide a high performance NPN bipolar transistor in parallel to fabrication of a PMOSFET and an NMOSFET. Gate and base contacts are formed in a first polysilicon layer. The base contacts are implanted with P+ ion concentrations for diffusing base contact regions of the substrate in a later drive-in step. Source and drain contacts and emitter contacts are formed in a second polysilicon layer. The source and drain contacts are formed as a unit and then separated into discrete contacts by a spin-on polymer planarization and etch-back procedure. Lightly-doped lateral margins of the source, drain and base regions are ion-implanted in an initial low concentration (e.g. about 10.sup.13 atoms/cm.sup.2). The gate and base contact structures serve as a mask to self-align the implants. Then, the gate and base structures are enclosed in an oxide box having sidewalls.
    Type: Grant
    Filed: August 19, 1987
    Date of Patent: February 20, 1990
    Assignee: Tektronix, Inc.
    Inventors: Jack Sachitano, Hee K. Park, Paul K. Boyer, Gregory C. Eiden, Tadanori Yamaguchi
  • Patent number: 4826782
    Abstract: An intermediate structure in the fabrication of a metal-oxide semiconductor field-effect transistor is made from a substrate of p+ silicon having an elongate insulated gate structure on its main face. First and second areas of the main face are exposed along first and second opposite sides respectively of the gate structure. Donor impurity atoms are introduced into the substrate by way of at least the first area of the main face, to achieve a predetermined concentration of electrons in a region of the substrate that is subjacent the first area of the main face. The gate structure is opague to the impurity atoms. A sidewall of silicon dioxide is formed along the first side of the gate structure, whereby a strip of the first area of the main face is covered by the sidewall and other parts of the first area remain exposed adjacent the sidewall.
    Type: Grant
    Filed: April 17, 1987
    Date of Patent: May 2, 1989
    Assignee: Tektronix, Inc.
    Inventors: Jack Sachitano, Paul K. Boyer, Hee K. Park, Gregory C. Eiden