Patents by Inventor Gregory C. Parrish

Gregory C. Parrish has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6950770
    Abstract: Various methods, systems and apparatuses having an integrated circuit that contains a calibration circuit having a series of delay elements to receive a reference signal. The reference signal establishes a standard unit of time. The calibration circuit also generates one or more calibrated delay signals derived from the reference signal. The one or more calibrated delay signals are precise to a known fraction of the standard unit of time.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: September 27, 2005
    Assignee: Intel Corporation
    Inventors: Gregory C. Parrish, Subrata Mandal
  • Publication number: 20040059533
    Abstract: Various methods, systems and apparatuses having an integrated circuit that contains a calibration circuit having a series of delay elements to receive a reference signal. The reference signal establishes a standard unit of time. The calibration circuit also generates one or more calibrated delay signals derived from the reference signal. The one or more calibrated delay signals are precise to a known fraction of the standard unit of time.
    Type: Application
    Filed: September 25, 2002
    Publication date: March 25, 2004
    Inventors: Gregory C. Parrish, Subrata Mandal
  • Publication number: 20030163774
    Abstract: An apparatus, system, and method to efficiently test a device under test by compression and decompression of test vectors and outputs.
    Type: Application
    Filed: February 26, 2002
    Publication date: August 28, 2003
    Inventor: Gregory C. Parrish
  • Patent number: 6288723
    Abstract: An apparatus and method for performing conversion of graphical data format is disclosed. A matrix multiplication is performed on a first set of data and a second set of data to generate a third set of data in a first format. The first and second sets of data represent the graphical data. The third set of data in the first format is transmitted to a graphics card. The third set of data in the first format is converted to a converted set of data in a second format.
    Type: Grant
    Filed: April 1, 1998
    Date of Patent: September 11, 2001
    Assignee: Intel Corporation
    Inventors: Thomas Huff, Shreekant S. Thakkar, Gregory C. Parrish
  • Patent number: 6115812
    Abstract: An apparatus and method for performing vertical parallel operations on packed data is described. A first set of data operands and a second set of data operands are accessed. Each of these sets of data represents graphical data stored in a first format. The first set of data operands is convereted into a converted set and the second set of data operands is replicated to generate a replicated set. A vertical matrix multiplication is performed on the converted set and the replicated set to generate transformed graphical data.
    Type: Grant
    Filed: April 1, 1998
    Date of Patent: September 5, 2000
    Assignee: Intel Corporation
    Inventors: Mohammad Abdallah, Thomas Huff, Gregory C. Parrish, Shreekant S. Thakkar
  • Patent number: 5638131
    Abstract: Successive pixels representing video data in successive lines in a raster scan are buffered. Each of the lines has a sync pulse defining the line beginning. A phase adjustment is determined between the sync pulse, preferably at a particular level in the sync pulse, and an adjacent one of system adjacent clock signals at a particular frequency. The actual or expected phase adjustment between the pixels at the end of each line is also determined. The difference between the phase adjustments at the beginning and end of each line is then determined. Progressive adjustments are made in the phase of each successive pixel in the line relative to the system clock signals in accordance with the number of system clock signals in the line and the determined difference in the phase adjustment between the line beginning and end. In this way, the pixels of video data are synchronized with the system clock signals.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: June 10, 1997
    Assignee: Brooktree Corporation
    Inventors: Gregory C. Parrish, Benjamin E. Felts, III, Sanjay K. Jha, David J. Wicker
  • Patent number: 5404173
    Abstract: Successive pixels representing video data in successive lines in a raster scan are buffered. Each of the lines has a sync pulse defining the line beginning. A phase adjustment is determined between the sync pulse, preferably at a particular level in the sync pulse, and an adjacent one of system adjacent clock signals at a particular frequency. The actual or expected phase adjustment between the pixels at the end of each line is also determined. The difference between the phase adjustments at the beginning and end of each line is then determined. Progressive adjustments are made in the phase of each successive pixel in the line relative to the system clock signals in accordance with the number of system clock signals in the line and the determined difference in the phase adjustment between the line beginning and end. In this way, the pixels of video data are synchronized with the system clock signals.
    Type: Grant
    Filed: March 10, 1993
    Date of Patent: April 4, 1995
    Assignee: Brooktree Corporation
    Inventors: Gregory C. Parrish, Benjamin E. Felts, III, Sanjay K. Jha, David J. Wicker