Abstract: Digital predistortion system, methods and circuitry for linearizing a non-linear element using a multiply partitioned architecture that first addresses long or “memory” effects, and separately addresses shorter duration effects. These blocks or circuits are operated with the non-linear element to provide a highly linear system. A first or long predistortion block receives a baseband signal input and includes a plurality of parallel memory blocks each including a programmable linearity, a digital filter, summers, multipliers and multiplexers with control signals for configuring the blocks to form filters of different types. A second or short predistortion block is coupled to the long predistortion block and comprises a generalized Nth order polynomial filter coupled to a programmable linear equalizer. The first predistorter block compensates for effects of a longer duration, and the second predistorter block compensates for effects of a shorter duration.

Abstract: An apparatus providing additional response for a distortion correcting device that receives a first signal at a correcting input and provides a first delayed output signal at an output includes: (a) A first signal combiner coupled with an input and the correcting input. (b) A delay unit coupled with the input provides a second delayed signal to a delayed signal terminal. (c) A second signal combiner coupled with the delayed signal terminal and the output employs the output signal and the second delayed signal to present an error signal at a first error terminal. (d) An adaptive circuit coupled with the input locus, the first signal combiner and the second signal combiner employs provides a supplemental signal to the first signal combiner which employs the input signal and the supplemental signal to present the first signal to reduce the error signal.

Abstract: One embodiment of the invention includes an amplifier system. The system comprises a digital predistortion (DPD) system configured to receive an input signal and to provide the input signal as a first digital signal component along a first amplifier path and a second digital signal component along a second amplifier path. The system also comprises a first digital-to-analog converter (DAC) configured to convert the first digital signal component to a first analog signal component and a second DAC configured to convert the second digital signal component to a second analog signal component. The system further comprises a Doherty amplifier comprising a main amplifier in the first amplifier path that is configured to amplify the first analog signal component and a peak amplifier in the second amplifier path that is configured to amplify the second analog signal component.

Abstract: System and method for preprocessing a signal for transmission by a power amplifier. In a preferred embodiment a multiple input multiple output processor is coupled to a plurality of power amplifiers for transmitting a signal, where the number of power amplifiers exceeds the number of antennas. The multiple input multiple output processor performs an algorithm to optimize the output vector ensuring that the transmit power for any one amplifier is below a predetermined threshold. In a preferred embodiment a Remez optimization algorithm is performed. Alternative optimization algorithms may be used. In a preferred embodiment the processor is a single integrated circuit. A method is disclosed where a multiple output vector is produced for transmission, using an optimization algorithm to produce an output vector that ensures that for any of the power amplifiers, the transmit power is maintained below a predetermined threshold.

Abstract: A method and apparatus for equalizing a received quadrature amplitude modulated signal is disclosed. To equalize the signal, a band edge equalizer (BEE) is used in combination with a symbol spaced equalizer (SSE) and possibly a decision feedback equalizer (DFE). The equalizer's are used along a series path to equalize the QAM signal in a series of equalization operations. By separating the equalization of the signal to separate equalizers, the cost of the equalization can be reduced without substantially affecting performance. In particular, band edge equalizing the QAM signal and symbol space equalizing the symbol can reduce the number of multiplies per second required by any particular equalizer. Accordingly, the equalizers used can be less expensive. Also, using a decimating circuit between the BEE and the SSE that decimates the sample rate of the signal being provided to the SSE can further reduce the number of multiplies per second that must be performed by the SSE.