Abstract: A linear systolic array of computation cells, each cell having several vector rotation stages. These stages are programmable to provide efficient implementation of a variety of matrix algorithms. All data movement between cells is via parameterized data packets, and the full linear systolic array is completely data flow driven at the packet level. Physical computation cells can be mapped to act as one or more logical computation cells, allowing a small array to function logically as a larger array through a logical folding. This mapping also allows defective cells to be bypassed for fault tolerance. The array can be used to compute adaptive weights in digital beamforming radar applications.

Abstract: A reconfigurable computer interface for use in interfacing a first subsystem to a second subsystem including a reconfigurable state machine mechanism for generating a plurality of interface control signals in accordance with a state table in response to a plurality of mode control signals. A first mechanism is included for generating the state table and a second mechanism is provided for generating the mode control signals with each transmitted to the reconfigurable state machine mechanism. In a preferred embodiment, an initiation logic device generates and downloads a state table and a plurality of mode control signals to a programmable state machine when the reconfigurable computer interface is utilized to connect a new external peripheral device to a signal processing system. The state table defines the characteristics of the state machine and the state machine controls the operation of the reconfigurable computer interface.

Abstract: An arithmetic element controller which provides for memory address generation for three independent memories of a signal processor and for direct memory access from external devices by way of an interface to the control and data store memories. The arithmetic element controller comprises a first address generator which includes a general purpose address generator circuit and three separate address generator circuits which generates memory addresses for data store, control store and micro store memories, respectively. A second address generator comprises two address generator circuit which comprise memory address logic that generate memory addresses that permit direct memory addressing of the control store and data store memories by way of the interface. A memory access controller is coupled to the two address generators to control access to the respective data store and control store memories by the respective address generators.