Patents by Inventor Gregory D. Rogers

Gregory D. Rogers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6944552
    Abstract: One embodiment of the invention is a method for analyzing power in a component comprising determining a plurality of current densities, wherein each current density is associated with one portion of a plurality of portions of the component, determining a plurality of wire densities, wherein each wire density is associated with one region of a plurality of regions of the component, and comparing the plurality of current densities and the plurality of wire densities.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: September 13, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Erin Francom, Gregory D. Rogers
  • Publication number: 20040268277
    Abstract: One embodiment of the invention is a method for analyzing power in a component comprising determining a plurality of current densities, wherein each current density is associated with one portion of a plurality of portions of the component, determining a plurality of wire densities, wherein each wire density is associated with one region of a plurality of regions of the component, and comparing the plurality of current densities and the plurality of power wire densities.
    Type: Application
    Filed: June 25, 2003
    Publication date: December 30, 2004
    Inventors: Erin Francom, Gregory D. Rogers
  • Publication number: 20040201631
    Abstract: When an operator enters a partial address into a browser, the browser displays at least one full address, where the displayed address may be an address that has not been previously entered into the browser or accessed by the browser.
    Type: Application
    Filed: January 31, 2002
    Publication date: October 14, 2004
    Inventors: S. Brandon Keller, Gregory D. Rogers, George H. Robbert
  • Publication number: 20030145046
    Abstract: When an operator enters a partial address into a browser, the browser displays at least one full address, where the displayed address may be an address that has not been previously entered into the browser or accessed by the browser.
    Type: Application
    Filed: January 31, 2002
    Publication date: July 31, 2003
    Inventors: S. Brandon Keller, Gregory D. Rogers, George H. Robbert
  • Publication number: 20030145065
    Abstract: When an operator enters a partial address into a browser, the browser displays at least one full address, where the displayed address may be an address that has not been previously entered into the browser or accessed by the browser.
    Type: Application
    Filed: January 31, 2002
    Publication date: July 31, 2003
    Inventors: S. Brandon Keller, Gregory D. Rogers, George H. Robbert
  • Publication number: 20030145112
    Abstract: When an operator enters a partial address into a browser, the browser displays at least one full address, where the displayed address may be an address that has not been previously entered into the browser or accessed by the browser.
    Type: Application
    Filed: January 31, 2002
    Publication date: July 31, 2003
    Inventors: S. Brandon Keller, Gregory D. Rogers, George H. Robbert
  • Publication number: 20030145087
    Abstract: When an operator enters a partial address into a browser, the browser displays at least one full address, where the displayed address may be an address that has not been previously entered into the browser or accessed by the browser.
    Type: Application
    Filed: January 31, 2002
    Publication date: July 31, 2003
    Inventors: S. Brandon Keller, Gregory D. Rogers, George H. Robbert
  • Patent number: 6502223
    Abstract: A method for simulating noise on the input of a static logic gate and determining noise on the output of the static logic gate. The method identifies the PFETs and NFETs that are used when a particular voltage pattern drives the input of a static gate. After the FETS have been identified, P/N ratios are calculated for all possible input combinations. A maximum or minimum P/N ratio may be chosen and a noise signal simulated on the input of the gate. The signal created on the output of this gate is noise that may be used to evaluate other circuits for noise problems. Using noise created by this method, integrated circuit designers can create computer simulations that better model the electrical environment that integrated circuits operate in.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: December 31, 2002
    Assignee: Hewlett-Packard Company
    Inventors: S Brandon Keller, Gregory D. Rogers
  • Publication number: 20020190745
    Abstract: A method for calculating the P/N ratios of static gates based on the voltages presented at the inputs of these static gates. The method identifies the PFETs and NFETs that are used when a particular voltage pattern drives the input of a static gate. After the FETS have been identified, a maximum and minimum P/N ratio is calculated. A maximum and minimum P/N ratio is determined in order provide more accurate models for simulating problems, for example, noise on the inputs. Using the P/N ratios created by this method, integrated circuit designers can create computer simulations that better model the electrical environment that integrated circuits operate in and most likely reduce the probability that the particular integrated circuit they are designing will have design errors.
    Type: Application
    Filed: April 30, 2001
    Publication date: December 19, 2002
    Inventors: S. Brandon Keller, Gregory D. Rogers
  • Publication number: 20020194573
    Abstract: A method for simulating noise on the input of a static logic gate and determining noise on the output of the static logic gate. The method identifies the PFETs and NFETs that are used when a particular voltage pattern drives the input of a static gate. After the FETS have been identified, P/N ratios are calculated for all possible input combinations. A maximum or minimum P/N ratio may be chosen and a noise signal simulated on the input of the gate. The signal created on the output of this gate is noise that may be used to evaluate other circuits for noise problems. Using noise created by this method, integrated circuit designers can create computer simulations that better model the electrical environment that integrated circuits operate in.
    Type: Application
    Filed: April 30, 2001
    Publication date: December 19, 2002
    Inventors: S. Brandon Keller, Gregory D. Rogers
  • Patent number: 6496031
    Abstract: A method for calculating the P/N ratios of static gates based on the voltages presented at the inputs of these static gates. The method identifies the PFETs and NFETs that are used when a particular voltage pattern drives the input of a static gate. After the FETS have been identified, a maximum and minimum P/N ratio is calculated. A maximum and minimum P/N ratio is determined in order provide more accurate models for simulating problems, for example, noise on the inputs. Using the PIN ratios created by this method, integrated circuit designers can create computer simulations that better model the electrical environment that integrated circuits operate in and most likely reduce the probability that the particular integrated circuit they are designing will have design errors.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: December 17, 2002
    Assignee: Hewlett-Packard Company
    Inventors: S Brandon Keller, Gregory D Rogers