Abstract: One embodiment of the invention is a method for analyzing power in a component comprising determining a plurality of current densities, wherein each current density is associated with one portion of a plurality of portions of the component, determining a plurality of wire densities, wherein each wire density is associated with one region of a plurality of regions of the component, and comparing the plurality of current densities and the plurality of wire densities.

Abstract: One embodiment of the invention is a method for analyzing power in a component comprising determining a plurality of current densities, wherein each current density is associated with one portion of a plurality of portions of the component, determining a plurality of wire densities, wherein each wire density is associated with one region of a plurality of regions of the component, and comparing the plurality of current densities and the plurality of power wire densities.

Abstract: When an operator enters a partial address into a browser, the browser displays at least one full address, where the displayed address may be an address that has not been previously entered into the browser or accessed by the browser.

Abstract: When an operator enters a partial address into a browser, the browser displays at least one full address, where the displayed address may be an address that has not been previously entered into the browser or accessed by the browser.

Abstract: When an operator enters a partial address into a browser, the browser displays at least one full address, where the displayed address may be an address that has not been previously entered into the browser or accessed by the browser.

Abstract: When an operator enters a partial address into a browser, the browser displays at least one full address, where the displayed address may be an address that has not been previously entered into the browser or accessed by the browser.

Abstract: When an operator enters a partial address into a browser, the browser displays at least one full address, where the displayed address may be an address that has not been previously entered into the browser or accessed by the browser.

Abstract: A method for simulating noise on the input of a static logic gate and determining noise on the output of the static logic gate. The method identifies the PFETs and NFETs that are used when a particular voltage pattern drives the input of a static gate. After the FETS have been identified, P/N ratios are calculated for all possible input combinations. A maximum or minimum P/N ratio may be chosen and a noise signal simulated on the input of the gate. The signal created on the output of this gate is noise that may be used to evaluate other circuits for noise problems. Using noise created by this method, integrated circuit designers can create computer simulations that better model the electrical environment that integrated circuits operate in.

Abstract: A method for calculating the P/N ratios of static gates based on the voltages presented at the inputs of these static gates. The method identifies the PFETs and NFETs that are used when a particular voltage pattern drives the input of a static gate. After the FETS have been identified, a maximum and minimum P/N ratio is calculated. A maximum and minimum P/N ratio is determined in order provide more accurate models for simulating problems, for example, noise on the inputs. Using the P/N ratios created by this method, integrated circuit designers can create computer simulations that better model the electrical environment that integrated circuits operate in and most likely reduce the probability that the particular integrated circuit they are designing will have design errors.

Abstract: A method for simulating noise on the input of a static logic gate and determining noise on the output of the static logic gate. The method identifies the PFETs and NFETs that are used when a particular voltage pattern drives the input of a static gate. After the FETS have been identified, P/N ratios are calculated for all possible input combinations. A maximum or minimum P/N ratio may be chosen and a noise signal simulated on the input of the gate. The signal created on the output of this gate is noise that may be used to evaluate other circuits for noise problems. Using noise created by this method, integrated circuit designers can create computer simulations that better model the electrical environment that integrated circuits operate in.

Abstract: A method for calculating the P/N ratios of static gates based on the voltages presented at the inputs of these static gates. The method identifies the PFETs and NFETs that are used when a particular voltage pattern drives the input of a static gate. After the FETS have been identified, a maximum and minimum P/N ratio is calculated. A maximum and minimum P/N ratio is determined in order provide more accurate models for simulating problems, for example, noise on the inputs. Using the PIN ratios created by this method, integrated circuit designers can create computer simulations that better model the electrical environment that integrated circuits operate in and most likely reduce the probability that the particular integrated circuit they are designing will have design errors.