Patents by Inventor Gregory D. Sabin
Gregory D. Sabin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6737745Abstract: The present invention is a method and structure for placing resistive circuits underneath a bonding pad in integrated circuit devices such that the resistive circuits are protected from shear and compressive stresses during bonding processes. The resistor is a serpentine wire pattern. A bonding pad is formed above the resistor such that the serpentine pattern extends over the entire bond pad area. The method and structure allow the formation of IC devices with smaller die areas.Type: GrantFiled: September 18, 2002Date of Patent: May 18, 2004Assignee: Intel CorporationInventors: Gregory D. Sabin, William J. Gross, Jung-Yueh Chang
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Patent number: 6734093Abstract: The present invention provides a bonding pad structure for integrated circuit devices which allows the active circuits to be placed under bonding pads of the device without affecting the performance of the active circuits. The bonding pad structure is composed of at least two metal layers overlying the active circuits so that the bonding pad may be subjected to thermal and mechanical stresses without damaging the underlying active circuits. The metal layer underlying the bonding pad is patterned and etched forming an array of openings in the metal that may take any shape, e.g. slots, grid, circles. The present invention enables a reduction in the chip area and eliminates the parasitic resistance due to long interconnection wires between bonding pads and active regions.Type: GrantFiled: March 17, 1999Date of Patent: May 11, 2004Assignee: Intel CorporationInventors: Gregory D. Sabin, William J. Gross, Jung-Yueh Chang
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Publication number: 20030017691Abstract: The present invention is a method and structure for placing resistive circuits underneath a bonding pad in integrated circuit devices such that the resistive circuits are protected from shear and compressive stresses during bonding processes. The resistor is a serpentine wire pattern. A bonding pad is formed above the resistor such that the serpentine pattern extends over the entire bond pad area. The method and structure allow the formation of IC devices with smaller die areas.Type: ApplicationFiled: September 18, 2002Publication date: January 23, 2003Inventors: Gregory D. Sabin, William J. Gross, Jung-Yueh Chang
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Patent number: 6486051Abstract: The present invention is a method and structure for placing resistive circuits underneath a bonding pad in integrated circuit devices such that the resistive circuits are protected from shear and compressive stresses during bonding processes. The resistor is a serpentine wire pattern. A bonding pad is formed above the resistor such that the serpentine pattern extends over the entire bond pad area. The method and structure allow the formation of IC devices with smaller die areas.Type: GrantFiled: March 17, 1999Date of Patent: November 26, 2002Assignee: Intel CorporationInventors: Gregory D. Sabin, William J. Gross, Jung-Yueh Chang
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Patent number: 5900770Abstract: A computer circuit comprising a driver circuit and a variable loading circuit coupled to the driver circuit. The variable loading circuit is configured to provide a first capacitive load to the output driver while operating according to a first state, and a second capacitive load while operating according to a second state. According to one embodiment, the variable loading circuit includes a first programmable cell element. The variable loading circuit is configured to operate according to the first state in response to the first programmable cell element being programmed. The variable loading circuit is further configured to operate according to the second state in response to the first programmable cell element being erased and a voltage potential being supplied.Type: GrantFiled: June 13, 1997Date of Patent: May 4, 1999Assignee: Intel CorporationInventor: Gregory D. Sabin
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Patent number: 5895443Abstract: The present invention provides test flow assurance using memory imprinting. The device being tested includes a nonvolatile memory portion for storing an information imprint in a present test status field. The imprint indicates the bin category to which the device is to be directed according to the results of a test sequence. During the start of a test in the test flow, the present test status field is read to determine whether the device has already passed through the present test. If so, the device is not retested according to that test step, and it is binned out according to the imprinted information. If the imprint indicates that the device has not already passed through the present test, then the present test sequence is performed, the device programmed with its imprint, and binned out accordingly.Type: GrantFiled: July 19, 1996Date of Patent: April 20, 1999Assignee: Intel CorporationInventors: William Gross, Jr., Gregory D. Sabin
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Patent number: 5703496Abstract: The output driver includes a plurality of transistor devices connected to an output line. In one arrangement, a separate flash-programmable element is connected to each of the plurality of transistor devices. Each of the separate flash elements receives the data signal along an input line and outputs the data signal if the flash cell is enabled (or not programmed) and outputs a constant voltage level, regardless of the data signal, if the flash element is not enabled. Hence, only those output transistors connected to flash elements that have been enabled are triggered by the output signal. Other transistors merely receive a constant voltage and are, therefore, not triggered regardless of the output signal. In another arrangement, the output driver is configured to forward output signals to all of the output transistors but the flash cells are programmed to adjust a time delay occurring prior to reception by the output transistors.Type: GrantFiled: March 28, 1996Date of Patent: December 30, 1997Assignee: Intel CorporationInventor: Gregory D. Sabin
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Patent number: 5638007Abstract: The output driver includes a plurality of transistor devices connected to an output line. A separate flash-programmable element is connected to each of the plurality of transistor devices. Each of the separate flash elements receives the data signal along an input line and outputs the data signal if the flash cell is enabled (or not programmed) and outputs a constant voltage level, regardless of the data signal, if the flash element is not enabled. Hence, only those output transistors connected to flash elements that have been enabled are triggered by the output signal. Other transistors merely receive a constant voltage and are, therefore, not triggered regardless of the output signal. By enabling only a few of the transistors, a current slew rate of current drawn through the transistors is reduced, thereby reducing overall voltage noise levels, although at the expense of slower signal throughput.Type: GrantFiled: September 26, 1995Date of Patent: June 10, 1997Assignee: Intel CorporationInventor: Gregory D. Sabin
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Patent number: 5603412Abstract: The present invention provides test flow assurance using memory imprinting. The device being tested includes a nonvolatile memory portion for storing an information imprint in a present test status field. The imprint indicates the bin category to which the device is to be directed according to the results of a test sequence. During the start of a test in the test flow, the present test status field is read to determine whether the device has already passed through the present test. If so, the device is not retested according to that test step, and it is binned out according to the imprinted information. If the imprint indicates that the device has not already passed through the present test, then the present test sequence is performed, the device programmed with its imprint, and binned out accordingly.Type: GrantFiled: February 2, 1996Date of Patent: February 18, 1997Assignee: INTEL CorporationInventors: William Gross, Jr., Gregory D. Sabin
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Patent number: 5538141Abstract: The present invention provides test flow assurance using memory imprinting. The device being tested includes a nonvolatile memory portion for storing an information imprint in a present test status field. The imprint indicates the bin category to which the device is to be directed according to the results of a test sequence. During the start of a test in the test flow, the present test status field is read to determine whether the device has already passed through the present test. If so, the device is not retested according to that test step, and it is binned out according to the imprinted information. If the imprint indicates that the device has not already passed through the present test, then the present test sequence is performed, the device programmed with its imprint, and binned out accordingly.Type: GrantFiled: September 27, 1994Date of Patent: July 23, 1996Assignee: INTEL CorporationInventors: William Gross, Jr., Gregory D. Sabin
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Patent number: RE41355Abstract: The present invention provides a bonding pad structure for integrated circuit devices which allows the active circuits to be placed under bonding pads of the device without affecting the performance of the active circuits. The bonding pad structure is composed of at least two metal layers overlying the active circuits so that the bonding pad may be subjected to thermal and mechanical stresses without damaging the underlying active circuits. The metal layer underlying the bonding pad is patterned and etched forming an array of openings in the metal that may take any shape, e.g. slots, grid, circles. The present invention enables a reduction in the chip area and eliminates the parasitic resistance due to long interconnection wires between bonding pads and active regions.Type: GrantFiled: May 5, 2006Date of Patent: May 25, 2010Assignee: Intel CorporationInventors: Gregory D. Sabin, William J. Gross, Jung-Yueh Chang