Patents by Inventor Gregory D. U'Ren

Gregory D. U'Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7580172
    Abstract: A microelectromechanical systems device having an electrical interconnect between circuitry outside the device and at least one of an electrode and a movable layer within the device. At least a portion of the electrical interconnect is formed from the same material as a conductive layer between the electrode and a mechanical layer of the device. In an embodiment, this conductive layer is a sacrificial layer that is subsequently removed to form a cavity between the electrode and the movable layer. The sacrificial layer is preferably formed of molybdenum, doped silicon, tungsten, or titanium. According to another embodiment, the conductive layer is a movable reflective layer that preferably comprises aluminum.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: August 25, 2009
    Assignee: Qualcomm Mems Technologies, Inc.
    Inventors: Alan G. Lewis, Manish Kothari, John Batey, Teruo Sasagawa, Ming-Hau Tung, Gregory D. U'Ren, Stephen Zee
  • Patent number: 7183627
    Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: February 27, 2007
    Assignee: Newport Fab, LLC
    Inventor: Gregory D. U'ren
  • Patent number: 7132700
    Abstract: A disclosed embodiment is a method for fabricating a structure in a semiconductor die, the method comprising depositing a silicon buffer layer over a single crystalline region and at least one isolation region at a first pressure, where the silicon buffer layer is continuous, i.e. comprises small poly grains, over the at least one isolation region. The method further includes forming a silicon germanium layer over the silicon buffer layer at a second pressure, where the silicon germanium layer is also continuous, i.e. comprises small poly grains, over the at least one isolation region. In one embodiment, the first pressure is less than the second pressure. In other embodiments, a structure is fabricated according to the above method.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: November 7, 2006
    Assignee: Newport Fab, LLC
    Inventors: Gregory D. U'Ren, Sy Vo
  • Patent number: 7078744
    Abstract: A disclosed embodiment is a method for fabricating an emitter structure, comprising a step of conformally depositing an undoped polysilicon layer in an emitter window opening and over a base. Next, a doped polysilicon layer is non-conformally deposited over the undoped layer. Thereafter, the steps of conformally depositing an undoped polysilicon layer and non-conformally depositing a doped polysilicon layer are repeated until the emitter window opening is filled. The method can further comprise a step of activating dopants. In another embodiment, an emitter structure is fabricated according to the above method.
    Type: Grant
    Filed: July 10, 2004
    Date of Patent: July 18, 2006
    Assignee: Newport Fab, LLC
    Inventor: Gregory D. U'Ren
  • Patent number: 7064073
    Abstract: According to one embodiment, a method for reducing contaminants in a reactor chamber is disclosed where the method comprises a step of etching the reactor chamber, which can comprise, for example, a dry etch process performed with hydrogen and HCL. Next, the reactor chamber is baked, which can comprise, for example, baking with hydrogen. Thereafter, an undoped semiconductor layer, such as an undoped silicon layer, is deposited in the reactor chamber to form a sacrificial semiconductor layer, for example, a sacrificial silicon layer. Then, the sacrificial semiconductor layer, for example, the sacrificial silicon layer, is removed from the reactor chamber. The removal step can comprise, for example, a dry etch process performed with HCL. In another embodiment, a wafer is fabricated in a reactor chamber that is substantially free of contaminants due to the implementation of the above method.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: June 20, 2006
    Assignee: Newport Fab, LLC
    Inventor: Gregory D. U'ren
  • Patent number: 6861308
    Abstract: A disclosed embodiment is a method for fabricating a SiGe layer, the method comprising depositing a silicon buffer layer over a single crystalline region and at least one isolation region at a first pressure, where the silicon buffer layer is continuous, i.e. comprises small poly grains, over the at least one isolation region. The method further includes forming a silicon germanium layer over the silicon buffer layer at a second pressure, where the silicon germanium layer is also continuous, i.e. comprises small poly grains, over the at least one isolation region. In one embodiment, the first pressure is less than the second pressure. In other embodiments, a structure is fabricated according to the above method.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: March 1, 2005
    Assignee: Newport Fab, LLC
    Inventors: Gregory D. U'Ren, Sy Vo
  • Publication number: 20040227157
    Abstract: A disclosed embodiment is a method for fabricating a SiGe layer, the method comprising depositing a silicon buffer layer over a single crystalline region and at least one isolation region at a first pressure, where the silicon buffer layer is continuous, i.e. comprises small poly grains, over the at least one isolation region. The method further includes forming a silicon germanium layer over the silicon buffer layer at a second pressure, where the silicon germanium layer is also continuous, i.e. comprises small poly grains, over the at least one isolation region. In one embodiment, the first pressure is less than the second pressure. In other embodiments, a structure is fabricated according to the above method.
    Type: Application
    Filed: May 13, 2003
    Publication date: November 18, 2004
    Applicant: Newport Fab, LLC dba Jazz Semiconductor
    Inventors: Gregory D. U'Ren, Sy Vo
  • Patent number: 6797578
    Abstract: A disclosed embodiment is a method for fabricating an emitter structure, comprising a step of conformally depositing an undoped polysilicon layer in an emitter window opening and over a base. Next, a doped polysilicon layer is non-conformally deposited over the undoped layer. Thereafter, the steps of conformally depositing an undoped polysilicon layer and non-conformally depositing a doped polysilicon layer are repeated until the emitter window opening is filled. The method can further comprise a step of activating dopants. In another embodiment, an emitter structure is fabricated according to the above method.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: September 28, 2004
    Assignee: Newport Fab, LLC
    Inventor: Gregory D. U'Ren
  • Patent number: 6580104
    Abstract: According to the disclosed method, the surface of a semiconductor wafer is covered by a protective oxide. The semiconductor wafer is then placed in a CVD reactor at a first temperature. Contaminants and the protective oxide are then removed from the surface of the semiconductor wafer at the first temperature. While contaminants and the protective oxide are being removed by the action of HCl and DCS, any silicon being removed from the surface of the silicon wafer, is being replenished so that there is no net change in the amount of silicon on the surface of the water. After removal of the contaminants and the protective oxide, epitaxial growth is performed on the surface of the semiconductor wafer at the first temperature. A structure comprising an epitaxially grown region can be fabricated according to the disclosed method.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: June 17, 2003
    Assignee: Newport Fab, LLC
    Inventor: Gregory D. U'Ren
  • Patent number: 6559022
    Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: May 6, 2003
    Assignee: Newport Fab, LLC
    Inventor: Gregory D. U'Ren
  • Patent number: 6514886
    Abstract: According to the disclosed method, the surface of a semiconductor wafer is covered by a protective oxide. For example, the protective oxide can be silicon oxide and the semiconductor wafer can be a silicon wafer. The semiconductor wafer is then placed in a CVD reactor at a first temperature. For example, the first temperature can be approximately 650° C. Contaminants and the protective oxide are then removed from the surface of the semiconductor wafer at the first temperature. For example, contaminants and the protective oxide can be removed from the surface of a silicon wafer by using an etchant, such as Hydrogen Chloride (HCl), and a precursor, such as Dichlorosilane (SiH2Cl2 or “DCS”), in appropriate proportions. While contaminants and the protective oxide are being removed by the action of HCl and DCS, any silicon being removed from the surface of the silicon wafer, is being replenished so that there is no net change in the amount of silicon on the surface of the wafer.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: February 4, 2003
    Assignee: Newport Fab, LLC
    Inventor: Gregory D. U'Ren
  • Publication number: 20020090788
    Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.
    Type: Application
    Filed: January 22, 2002
    Publication date: July 11, 2002
    Applicant: Conexant Systems, Inc.
    Inventor: Gregory D. U'ren
  • Publication number: 20020061628
    Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.
    Type: Application
    Filed: January 22, 2002
    Publication date: May 23, 2002
    Applicant: Conexant Systems, Inc.
    Inventor: Gregory D. U'Ren
  • Patent number: 6365479
    Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: April 2, 2002
    Assignee: Conexant Systems, Inc.
    Inventor: Gregory D. U'Ren