Abstract: A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.

Abstract: A nonvolatile memory residing on a single substrate is described. The nonvolatile memory includes a memory array having at least a memory cell. The memory cell includes a drain region, a source region, a control gate, and a floating gate. A drain programming voltage generation circuit is coupled to a programming voltage source and the drain region of the memory cell for providing a drain programming voltage to the drain region of the memory cell during programming of the memory cell. A control circuit is coupled to the drain programming voltage generation circuit for causing the drain programming voltage to vary with respect to a programming ability of the memory cell such that the memory cell is programmed to be within a predetermined range of a predetermined threshold voltage with a predetermined gate programming voltage for a predetermined programming time.

Abstract: A circuit for switching the source regions of reference devices used in a flash EPROM from ground potential to a potential of 3.5 volts during programming. This prevents charging of the floating gates of the reference devices on the selected word line and the discharging of the floating gates of the reference devices on the non-selected word lines.

Abstract: A reference scheme for verifying the erasing and programming in an electrically erasable and electrically programmable read-only memory fabricated on a silicon substrate which employs a plurality of memory cells, each of which contains a floating gate. The reference scheme employs trimmable single cell reference devices for both the erase verify and program verify operations. The threshold voltages of the reference cells are trimmed to a level below (in the case of the erase verify reference cell) or above (in the case of the program verify reference cell) which all memory cells in the array will be considered in a particular program state (i.e., erased or programmed). In the case of the read reference device, a double-cell read referencing device combining the erase and program verify reference cells is described. Although, the double-cell referencing device is preferred, a trimmable read reference device is also taught.

Abstract: A non-volatile memory device is described. The memory device includes a global bit line, a first block, and a second block. The first block includes a first memory cell having a drain region, a source region, a floating gate and a control gate. A first word line is coupled to the control gate of the first memory cell. A first local bit line is coupled to the drain region of the first memory cell. A first selecting means couples the first local bit line to the global bit line. The second block includes a second memory cell having a drain region, a source region, a floating gate and a control gate. A second word line is coupled to the control gate of the second memory cell. A second local bit line is coupled to the drain region of the second memory cell. A second selecting means couples the second local bit line to the global bit line.

Abstract: A non-volatile memory device is described. The memory device includes a first block and a second block. The first block includes a first memory cell having a drain region, a source region, a floating gate, and a control gate. A first word line is coupled to the control gate of the first memory cell. The second block includes a second memory cell having a drain region, a source region, a floating gate, and a control gate. A second word line is coupled to the control gate of the second memory cell. A bit line is coupled to the drain region of the first and the second memory cell. A refresh control means performs a refresh operation on one of the first and second memory cell. A sensing means is coupled to the bit line, and has a first reference potential and a second reference potential for detecting a voltage state of the first and second memory cell during the refresh operation.

Abstract: A method of repairing overerased cells in a flash memory array including a column having a first cell and a second cell is described. Repair begins by determining whether a first cell is overerased and applying a programming pulse if so. Next, the second cell is examined to determine whether it is overerased. A programming pulse is applied to the second cell if it is overerased. Afterward, if either of the cells was overerased then the repair pulse voltage level is incremented. These steps are repeated until none of the cells on the column is identified as overerased.

Abstract: A method of reprogramming field-effect memory cells of a memory array of an electrically erasable flash memory device is described. Each cell has a drain, a source, and a control gate. The drains of the cells are electrically connected to a bit line of the memory array. The cells are programmed and erased. The cells are repaired by grounding the sources and the control gates and taking the bit line to a predetermined potential. The memory array is selectively programmed. Other embodiments include repairing field-effect memory cells connected to a source line or part of a word line. Verification may be done between the repair step and selectively programming step.

Abstract: A method of forming a doped region within a monocrystalline silicon layer of an integrated circuit having an electrically erasable and electrically programmable memory device on a semiconductor substrate, wherein the doped region lies within a channel region near a drain region, but does not lie within a source region. After a patterned layer is formed over the channel region, the substrate is doped by ion implantation with a first dopant at a tilt angle no less than a minimum tilt angle and at about a predetermined azimuthal angle, such that a significant number of ions enter a drain region and a channel region near the drain region and substantially no ions enter a source region. The first dopant is the same dopant type as the monocrystalline silicon layer dopant. The drain region is masked. The source region is doped with a second dopant. The second dopant is an opposite dopant type as the monocrystalline silicon layer dopant. The source region and the drain region are doped with a third dopant.

Abstract: A flash EPROM memory array having vertical blocking is described. The array is organized into a plurality of vertical (column) blocks. Each block includes a source region switch which couples all the source regions in the memory cells in its respective block to a programming potential, ground or a disturb inhibit potential. Each of the blocks may be erased without disturbing the programming in the other blocks.

Abstract: A virtual ground electrically programmable read-only memory device in which disturbance to neighboring cells is practically eliminated, is disclosed. In one embodiment the memory device comprises a plurality of memory cells formed in a semiconductor substrate and arranged in rows and columns so as to form an array. During read operations, pairs of adjacent cells are accessed simultaneously by grounding a single column line within the array. The two adjacent column lines--one on each side of the grounded column line--are coupled to separate read paths. Within the array, rows of cells store bits from a plurality of data bytes according to a pattern in which pairs of adjacent cells store different bits from different bytes.