Abstract: A network processor is described that includes a network reference clock processor module for providing an at least substantially low-jitter, low-wander reference signal. In one or more embodiments, the network reference clock processor module includes a digital phase locked loop configured to at least substantially attenuate a wander noise portion from a reference signal. The network reference clock processor module also includes an analog phase locked loop communicatively coupled to the digital phase locked loop and configured to receive the reference signal from the digital phase locked loop. The analog phase locked loop is configured to attenuate a jitter noise portion having a first frequency characteristic from the reference signal and to provide the reference signal to a transceiver communicatively coupled to the analog phase locked loop. The transceiver is configured to attenuate a jitter noise portion having a second frequency characteristic from the reference signal.

Abstract: A phase-locked loop (PLL), a method of programmably adjusting a phase of a reference clock signal and a synchronous sequential logic circuit incorporating the PLL or the method. In one embodiment, the PLL includes: (1) a digital feedback delay line having a plurality of taps and (2) tap selection logic, coupled to the digital feedback delay line, for activating one of the plurality of taps and thereby insert a corresponding delay into the PLL.

Abstract: A phase-locked loop (PLL), a method of programmably adjusting a phase of a reference clock signal and a synchronous sequential logic circuit incorporating the PLL or the method. In one embodiment, the PLL includes: (1) a digital feedback delay line having a plurality of taps and (2) tap selection logic, coupled to the digital feedback delay line, for activating one of the plurality of taps and thereby insert a corresponding delay into the PLL.

Abstract: A method and apparatus are disclosed for sending and receiving logic signals. A driver is connected to a first end of a transmission line with a predetermined impedance and first and second transmission line ends for communicating the logic signals. The driver has a source for sending the logic signals, and a reference generator connected to the source for setting the magnitude of the signals sent by the source. A receiver is connected to the second transmission line end, and has a transmission line terminator for sinking the signals, and a reference generator connected to the terminator for setting a bias of the terminator to establish a certain family of terminator impedances for sinking the signals. The driver reference generator and the receiver reference generator interactively match the terminator impedance to the transmission line for the set magnitude of the signals.

Abstract: A method and apparatus are disclosed for sending and receiving logic signals responsive to external digital data input and control signals. A reference circuit providing a first and second reference signal is common to the signal generating and receiving circuitry. The signal generating circuitry includes a signal source connected to the transmission line for generating a variable level digital signal, and a reference level adjusting and switching circuit ("RLA/S circuit") which is responsive to the digital data input and the first reference signal. The RLA/S circuit is connected to the signal source for selecting the level of the variable level digital signal and providing a switching signal. The signal source output is thus adjusted and switched so that the signal source generates a digital signal to the transmission line which follows the digital data input at the selected output signal level.

Abstract: A system and method makes use of the line-in, line-out connectors for each right and left stereo channel of an audio card to provide a communications network. The distributed computers are connected in a master/slave configuration. All of the slave systems have the line-in ports, and the line-out ports, connected together. The master system line-out is connected to each slave system line-in port, and the slave system line-out ports are connected to the master line-in port, for each channel. A communications protocol is provided wherein the master system allows audio and data information to be simultaneously transferred between the master and slave systems. The master provides a clock signal and performs arbitration in order to facilitate the information transfer.

Abstract: The method and apparatus of the present invention permit the visual inspection of electronic component leads during the mounting thereof. A hot bar thermode or other mounting tool is provided having a plurality of thermally activatable blades. A vacuum chuck and associated vacuum pump are utilized to selectively mount an integrated circuit device such that the conductive leads of the device are disposed adjacent to the lower surfaces of the thermally activatable blades. A low angle light source is then utilized to illuminate the integrated circuit device conductive leads such that a high contrast is created between the conductive leads and the lower surface of the thermally activatable blades, in order to permit an accurate visual inspection of the conductive leads.

Abstract: A method and apparatus utilizing one or two cameras are described for visually inspecting a polygonal component located at the end of the robotic end effector for determining presence, position and orientation of component leads prior to placement. Image processing improvements are provided for decreasing computational complexity by representing two dimensional image areas of interest, and each containing leads along one side of a component, by one dimensional summation profiles.