Patents by Inventor Gregory E. Dermer
Gregory E. Dermer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8745306Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: GrantFiled: August 21, 2012Date of Patent: June 3, 2014Assignee: Intel CorporationInventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Publication number: 20120317328Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: ApplicationFiled: August 21, 2012Publication date: December 13, 2012Inventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Patent number: 8255605Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BICS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: GrantFiled: March 30, 2011Date of Patent: August 28, 2012Assignee: Intel CorporationInventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H Hofsheier, Nitin Y. Borkar
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Publication number: 20110185101Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: ApplicationFiled: March 30, 2011Publication date: July 28, 2011Inventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Patent number: 7930464Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: GrantFiled: August 28, 2009Date of Patent: April 19, 2011Assignee: Intel CorporationInventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Publication number: 20090319717Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: ApplicationFiled: August 28, 2009Publication date: December 24, 2009Inventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Patent number: 7603508Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: GrantFiled: January 14, 2008Date of Patent: October 13, 2009Assignee: Intel CorporationInventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Patent number: 7343442Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: GrantFiled: June 6, 2006Date of Patent: March 11, 2008Assignee: Intel CorporationInventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Patent number: 7058750Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.Type: GrantFiled: May 10, 2000Date of Patent: June 6, 2006Assignee: Intel CorporationInventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
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Patent number: 6798265Abstract: A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.Type: GrantFiled: April 25, 2002Date of Patent: September 28, 2004Assignee: Intel CorporationInventors: Rajendran Nair, Gregory E. Dermer, Stephen R. Mooney, Nitin Y. Borkar
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Publication number: 20020125930Abstract: A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.Type: ApplicationFiled: April 25, 2002Publication date: September 12, 2002Applicant: Intel CorporationInventors: Rajendran Nair, Gregory E. Dermer, Stephen R. Mooney, Nitin Y. Borkar
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Patent number: 6415388Abstract: A method and apparatus for power throttling in a microprocessor. A voltage source supplies voltage to the microprocessor, and a clock source operates the microprocessor at a desired frequency. In one embodiment, a power monitor is configured to measure the short term power consumption of the microprocessor. In another embodiment, a temperature sensor measures the temperature of the microprocessor. Control logic is coupled to the voltage source and the clock source. The control logic receives an indication of the power consumption or temperature, as applicable, and compares it to a predetermined value. In response to the comparison, the control logic varies the supply voltage and the frequency.Type: GrantFiled: October 30, 1998Date of Patent: July 2, 2002Assignee: Intel CorporationInventors: Chris S. Browning, Shekhar Y. Borkar, Gregory E. Dermer
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Patent number: 6411151Abstract: A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.Type: GrantFiled: December 13, 1999Date of Patent: June 25, 2002Assignee: Inter CorporationInventors: Rajendran Nair, Gregory E. Dermer, Stephen R. Mooney, Nitin Y. Borkar
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Patent number: 6330680Abstract: A method and apparatus for power throttling in a microprocessor. A voltage source supplies voltage to the microprocessor, and a clock source operates the microprocessor at a desired frequency. In one embodiment, a power monitor is configured to measure the short term power consumption of the microprocessor. In another embodiment, a temperature sensor measures the temperature of the microprocessor. Control logic is coupled to the voltage source and the clock source. The control logic receives an indication of the power consumption or temperature, as applicable, and compares it to a predetermined value. In response to the comparison, the control logic varies the supply voltage and the frequency.Type: GrantFiled: October 30, 1998Date of Patent: December 11, 2001Assignee: Intel CorporationInventors: Chris S. Browning, Shekhar Y. Borkar, Gregory E. Dermer
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Patent number: 4774659Abstract: A system and method for implementing virtual memory in a computer system, wherein a table containing entries indicative of the correlation of virtual memory addresses to physical memory addresses is maintained in main memory, and translation descriptors, derived from the translation table entries, for a variable group of virtual addresses, is maintained in a high speed memory. Portions of a virtual address to be translated are compared to the translation descriptors in the high speed memory. If a matching translation descriptor is found, the corresponding physical address is determined by combining a portion of the virtual address with a portion of the matching translation descriptor. If a matching descriptor is not found, a software algorithm is employed to generate a translation descriptor for the virtual address from the table in main memory. The generated translation descriptor is then installed in the high speed memory, the comparison repeated, and the corresponding physical address generated.Type: GrantFiled: April 16, 1986Date of Patent: September 27, 1988Assignee: Astronautics Corporation of AmericaInventors: James E. Smith, Gregory E. Dermer, Michael A. Goldsmith