Abstract: Various aspects of the present invention are directed to design modeling and/or processing of streaming data. According to an example embodiment, a system to model a hardware specification includes a platform (106) arranged to receive an input data stream and transmit an output data stream. The system also includes a source (102) for a streaming application adapted to provide the input data stream at a source data rate, a destination (104) for the streaming application adapted to consume the output data stream at a destination data rate, and a data channel (110) coupling the platform and a computer (108). The computer uses the hardware specification to generate intermediate data streams, which, in turn, are used to streamline the modeling for the platform.

Abstract: A high-speed parallel data communication approach overcomes data skewing concerns by concurrently transmitting data in a plurality of multiple-bit groups and, after receiving the concurrently-transmitted data, realigning skew-caused misalignments between the groups. In one particular example embodiment, for each group, an arrangement transfers the data in parallel and along with a clock signal for synchronizing digital data. The transferred digital data is synchronously collected via the clock signal for the group. At the receiving module, the data collected for each group is aligned using each group's dedicated clock signal. Skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.

Abstract: A circuit arrangement including a test-traffic generator, and adapted to communicate test-traffic onto a digital data path having other traffic sources. A first embodiment includes a data-generation circuit, a memory arrangement, state machine circuitry, and a status and feedback circuit. The memory arrangement stores a plurality of programmable commands indicative the type, pattern and behavior-in-time of the test-traffic. The data-generation circuit provides a data stream to the state machine circuitry, where the state machine assembles portions of the data stream into test-traffic having type, pattern and behavior-in-time characteristics selected responsive to the programmable commands. The state machine generates test-traffic on the digital data path. The status and feedback circuit monitors the digital data path for test-traffic, verifies the test-traffic against the data stream, and generates a feedback signal indicative of test-traffic quality or throughput.

Abstract: An adaptive data communication approach permits communication bus monitoring by using a reconfigurable bus monitor built into the CPU bus structure and adapted to report back to the CPU in response to detecting certain CPU-programmed events. In one particular example embodiment, a circuit arrangement having a CPU circuit communicates with another device over a communication channel while a reconfigurable circuit monitors the communication channel. The CPU circuit configures the reconfigurable circuit for monitoring any of various types of event expected to occur on the communication channel. The reconfigurable circuit collects signals passed on the communication channel and reports back to the CPU circuit when data indicative of the first event type occurs on the communication channel.

Abstract: A high-speed parallel-data communication approach overcomes skewing problems by transferring digital data with automatic realignment. In one example embodiment, a parallel bus has parallel bus lines adapted to transfer digital data from a data file, along with a synchronizing clock signal. To calibrate the synchronization, the sending module transfers synchronization codes which are sampled and validated according to an edge of the clock signal by a receiving module and then used to time-adjust the edge of the clock signal relative to the synchronization codes. The synchronization codes are implemented to toggle the bus lines with each of the synchronization codes transferred.

Abstract: In one example embodiment, a high-speed parallel-data communication approach transfers digital data in parallel from a first module to a second module over a communication channel including a plurality of parallel data-carrying lines and a clock path. The parallel bus lines are arranged in a plurality of groups, each of the groups including a plurality of data-carrying lines and a clock path adapted to carry a clock signal for synchronizing digital data carried from the first module to the second module. The sets of data are concurrently transferred using the groups of lines of the parallel bus, and at the second module and for each group, the transferred digital data is synchronously collected via the clock signal for the group. At the second module, the data collected for each group is aligned.

Abstract: A first in, first out (FIFO) circular buffer enables high speed streaming data transfer between integrated circuit devices by performing more than one data element transfer unidirectionally by having a plurality of ports to address a memory array. In addition, the multiple transfers are performed during one bus cycle and the number of transfers may be selectable. FIFO control circuitry limits the number of data elements transferred in response to the state of the memory array including almost empty or almost full.

Abstract: The operability and scaleability of electronic circuits is improved using a circuit arrangement that is modular, scaleable, straightforward to implement and allows for simple and safe physical design implementation. According to one example embodiment of the present invention, a reset method and system are used to effect a reset at several peripheral devices that may employ similar and/or different reset strategies. A reset module is coupled to a clock module having an external clock reference and to each of the peripheral devices. Operationally, the clock module provides a functional clock signal to each of the peripheral devices at one of a plurality of first frequencies. The reset module generates an internal reset signal in response to a system reset signal. In response to an internal reset signal, the clock module drives a common reset clock signal, having a reset clock frequency, to each of the peripheral devices via clock outputs at the clock module.

Abstract: A high-speed parallel data communication approach overcomes data skewing concerns by concurrently transmitting data in a plurality of multiple-bit groups and, after receiving the concurrently-transmitted data, realigning skew-caused misalignments between the groups. In one particular example embodiment, for each group, an arrangement transfers the data in parallel and along with a clock signal for synchronizing digital data. The transferred digital data is synchronously collected via the clock signal for the group. At the receiving module, the data collected for each group is aligned using each group's dedicated clock signal. Skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.

Abstract: A circuit arrangement including a test-traffic generator, and adapted to communicate test-traffic onto a digital data path having other traffic sources. A first embodiment includes a data-generation circuit, a memory arrangement, state machine circuitry, and a status and feedback circuit. The memory arrangement stores a plurality of programmable commands indicative the type, pattern and behavior-in-time of the test-traffic. The data-generation circuit provides a data stream to the state machine circuitry, where the state machine assembles portions of the data stream into test-traffic having type, pattern and behavior-in-time characteristics selected responsive to the programmable commands. The state machine generates test-traffic on the digital data path. The status and feedback circuit monitors the digital data path for test-traffic, verifies the test-traffic against the data stream, and generates a feedback signal indicative of test-traffic quality or throughput.

Abstract: An adaptive data communication approach permits communication bus monitoring by using a reconfigurable bus monitor built into the CPU bus structure and adapted to report back to the CPU in response to detecting certain CPU-programmed events. In one particular example embodiment, a circuit arrangement having a CPU circuit communicates with another device over a communication channel while a reconfigurable circuit monitors the communication channel. The CPU circuit configures the reconfigurable circuit for monitoring any of various types of event expected to occur on the communication channel. The reconfigurable circuit collects signals passed on the communication channel and reports back to the CPU circuit when data indicative of the first event type occurs on the communication channel.

Abstract: The operability and scaleability of electronic circuits is improved using a circuit arrangement that is modular, scaleable, straightforward to implement and allows for simple and safe physical design implementation. According to one example embodiment of the present invention, a reset method and system are used to effect a reset at several peripheral devices that may employ similar and/or different reset strategies. A reset module is coupled to a clock module having an external clock reference and to each of the peripheral devices. Operationally, the clock module provides a functional clock signal to each of the peripheral devices at one of a plurality of first frequencies. The reset module generates an internal reset signal in response to a system reset signal. In response to an internal reset signal, the clock module drives a common reset clock signal, having a reset clock frequency, to each of the peripheral devices via clock outputs at the clock module.

Abstract: A method of designing a mask-programmable random-access read-only memory device begins with a step of assigning weightings to addresses according to their expected frequency of access. These weighting are used in a second step of determining for each sense amplifier, what is the low-power sense (inverted or uninverted) of the stored bits using that sense amplifier as an output. The third step involves storing the data in the low-power sense. The fourth step involves inverting the outputs for the data that is stored inverted. This can involve using sense inverting sense amplifiers for inverted data and sense preserving amplifiers for uninverted data. The method can result in memories in which some outputs are sense inverting while others are sense preserving. The result is a memory device with reduced power consumption relative to a comparable design not taking advantage of the relationship between data values and power consumption.

Abstract: A first in, first out (FIFO) circular buffer enables high speed streaming data transfer between integrated circuit devices by performing more than one data element transfer unidirectionally by having a plurality of ports to address a memory array. In addition, the multiple transfers are performed during one bus cycle and the number of transfers may be selectable. FIFO control circuitry limits the number of data elements transferred in response to the state of the memory array including almost empty or almost full.

Abstract: In one example embodiment, a high-speed parallel-data communication approach transfers digital data in parallel from a first module to a second module over a communication channel including a plurality of parallel data-carrying lines and a clock path. The parallel bus lines are arranged in a plurality of groups, each of the groups including a plurality of data-carrying lines and a clock path adapted to carry a clock signal for synchronizing digital data carried from the first module to the second module. The sets of data are concurrently transferred using the groups of lines of the parallel bus, and at the second module and for each group, the transferred digital data is synchronously collected via the clock signal for the group. At the second module, the data collected for each group is aligned.

Abstract: A high-speed parallel-data communication approach overcomes skewing problems by transferring digital data with automatic realignment. In one example embodiment, a parallel bus has parallel bus lines adapted to transfer digital data from a data file, along with a synchronizing clock signal. To calibrate the synchronization, the sending module transfers synchronization codes which are sampled and validated according to an edge of the clock signal by a receiving module and then used to time-adjust the edge of the clock signal relative to the synchronization codes. The synchronization codes are implemented to toggle the bus lines with each of the synchronization codes transferred.

Abstract: A method in accordance with the present invention for developing an integrated circuit design using a compilation tool includes: (A) developing at least one HDL template by: (a) creating the HDL template; (b) creating a parameter file and a parameter check file for the HDL template; and (c) encrypting the HDL template; (B) developing design specifications for use in creating HDL for synthesis and for use in compiling one or more macro blocks; (C) creating the HDL for synthesis; and (D) creating netlists for at least one macro block instantiated in the HDL template using the design specifications. A development tool of the present invention implements the method on a computer system to form a portion of an integrated circuit fabrication system.

Abstract: A GTL input receiver for receiving differential GTL signals and for generating a CMOS output at a single-ended output terminal includes a comparator circuit, a current-to-voltage converter circuit, and an inverter. The comparator is formed of a first primary current steering device and a second primary current steering device. Auxiliary current steering devices are coupled to the first and second primary current steering devices for adding hysteresis by dynamically changing the ratio of the currents flowing through the first and second primary current source devices. The input receiver also includes a control circuit for selectively enabling and disabling the secondary current steering devices. As a result, the GTL input receiver has a hysteresis in the range of 50 mV to 200 mV and higher.