Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for inverter based return-to-zero (RZ)+non-RZ (NRZ) signaling. The interface circuit contains multiple ganged drivers (some or all of them are turned on at one point of time) and edge detection circuitry (to configure/modulate edges of the input data signal). These two circuits together generate weighted return-to-zero (RZ)+non-RZ (NRZ) signal.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for inverter based return-to-zero (RZ)+non-RZ (NRZ) signaling. The interface circuit contains multiple ganged drivers (some or all of them are turned on at one point of time) and edge detection circuitry (to configure/modulate edges of the input data signal). These two circuits together generate weighted return-to-zero (RZ)+non-RZ (NRZ) signal.

Abstract: A two phase clock generation circuit uses a current mirror and a crossbar switch to generate true and complement output clock signals that are relatively insensitive to process, voltage, and temperature variations. The current mirror generates a charging current and a discharging current that have a fixed magnitude ratio. The crossbar switch then alternately couples the charging current and the discharging current to the true and complement outputs of the clock generation circuit to generate the output clock signals. A selection signal generation unit is provided for generating the selection signal(s) required to appropriately control the switch. Because the charging and discharging currents are at fixed magnitudes and the crossbar switch is a balanced structure, the output clock signals remain aligned to a high degree of accuracy over a wide variety of conditions.