Abstract: The invention uses hydrogen ambient atmosphere to directly form PdGe contacts on Group III-V materials. Specific GaAs HBT's have been formed in a 100% H.sub.2 ambient, and demonstrate low etch reactivity attributable to the significant incorporation of hydrogen. The LP-MOCVD method used to demonstrate the invention produced a specific contact resistivity of less than 1.times.10.sup.-7 .OMEGA.-cm-.sup.-2, at preferred conditions of a 100% hydrogen ambient, 300.degree. C., and 15 minute reaction time. This is believed to be the lowest known resistance of any alloy method employed for PdGe on GaAs. Equally significant, the contacts demonstrate increased durability during etching.

Abstract: A reduced temperature low pressure metal organic chemical vapor deposition process for the production of semi-insulating deep level impurity undoped Group III-V phosphorous containing epitaxial layers. The present invention achieves production of semi-insulating layers at reduced growth temperatures in the approximate range of 490.degree. C. to 530.degree. C. Semi-insulating resistivities on the order of 10.sup.6 ohm-cm to 10.sup.9 ohm-cm are obtained according to the present process without resort to use of extrinsic dopants such as the transition metals typically used in conventional processes to obtain semi-insulating phosphorous containing layers, and without post processing annealing.

Abstract: A process for growing semi-insulating layers of indium phosphide and other group III-V materials through the use of halide dopant or etchant introduction during growth. Gas phase epitaxial growth techniques are utilized at low temperatures to produce indium phosphide layers having a resistivity greater than approximately 10.sup.7 ohm-cm. According to the preferred embodiment carbon tetrachloride is used as a dopant at flow rates above 5 sccm to grow the layers with substrate growth temperatures ranging from approximately 460.degree. C. to 525.degree. C. This temperature range provides an advantage over the transition metal techniques for doping indium phosphide since the high temperatures generally required for those techniques limit the ability to control growth. Good surface morphology is also obtained through the growth according to the present invention. The process may be used to form many types of group III-V semiconductor devices.

Abstract: An process for efficient controlled N-type silicon doping of Group III-V materials. Through the present invention silicon may be introduced into Group III-V materials at incorporation efficiencies in excess of 10.sup.-4. In a preferred embodiment doping with silicon tetrabromide attains incorporation efficiencies of approximately 0.37. Silicon incorporation efficiencies of approximately 1 should be obtained using silicon tetraiodide. The silicon dopant sources of the present invention may be used to accurately selectively produce net electron concentrations varying from approximately 1.times.10.sup.16 to 1.2.times.10.sup.20 cm.sup.-3. Favorable room temperature vapor pressures of the dopants used in accordance with the present invention allow for production of abrupt doping profiles. Additionally, high photoluminescence peak values, and low contact and sheet resistances are obtained through the present invention.