Abstract: A system and method avoids deadlock, such as circular routing deadlock, in a computer system by providing a virtual buffer at main memory. The computer system has an interconnection network that couples a plurality of processors having access to main memory. The interconnection network includes one or more routing agents each having at least one buffer for storing packets that are to be forwarded. When the routing agent's buffer becomes full, thereby preventing it from accepting any additional packets, the routing agent transfers at least one packet into the virtual buffer. By transferring a packet out of the buffer, the routing agent frees up space allowing it to accept a new packet. If the newly accepted packet also results in the buffer becoming full, another packet is transferred into the virtual buffer. This process is repeated until the deadlock condition is resolved. Packets are then retrieved from the virtual buffer.

Abstract: The invention provides a system and method for resolving ambiguous invalidate messages received by an entity of a computer system. An invalidate message is considered ambiguous when the receiving entity cannot tell whether it applies to a previously victimized memory block or to a memory block that the entity is waiting to receive. When an entity receives such an invalidate message, it stores the message in its miss address file (MAF). When the entity subsequently receives the memory block, the entity “replays” the Invalidate message from its MAF by invalidating the block from its cache and issuing an Acknowledgement (Ack) to the entity that triggered issuance of the Invalidate message command.

Abstract: A directory maintains status information over memory blocks in a shared memory computer system. The directory has a plurality of entries each corresponding to a respective block, and is organized into a main region and a write-back region. The main region has an owner field, identifying the current owner of the block. The write-back region has a writer field identifying the last owner to have written the block back to memory. To write a block back to memory, the owner enters its identifier in the writer field and writes the data back to memory without checking nor modifying the owner field. In response to a memory operation, if the contents of the owner field and the writer field match, memory concludes that it is the owner, otherwise memory concludes that the entity identified in the owner field is the owner.

Abstract: A system permits unacknowledged write backs in a computer. The computer has a plurality of processors and a shared memory. The shared memory stores data in terms of memory blocks, and each processor has a cache. Associated with each cache line is a tag containing the address of the block at that line, and its state. A duplicate copy of the tag information (DTAG) for each processor cache is also provided, and each section of the DTAG that corresponds to a given processor is organized into a primary DTAG region and a secondary DTAG region. The secondary DTAG region preferably stores tag information for a dirty version of a block, while the write back of the block is in flight to memory. This frees the primary DTAG region to store tag information for a block other than the dirty block, but using the same cache line.

Abstract: A channel-based mechanism resolves race conditions in a computer system between a first processor writing modified data back to memory and a second processor trying to obtain a copy of the modified data. In addition to a Q0 channel for carrying requests for data, a Q1 channel for carrying probes in response to Q0 requests, and a Q2 channel for carrying responses to Q0 requests, a new channel, the QWB channel, which has a higher priority than Q1 but lower than Q2, is also defined. When a forwarded Read command from the second processor results in a miss at the first processor's cache, because the requested memory block was written back to memory, a Loop command is issued to memory by the first processor on the QWB virtual channel. In response to the Loop command, memory sends the written back version of the memory block to the second processor.

Abstract: The invention provides a system and method for resolving ambiguous invalidate messages received by an entity of a computer system. An invalidate message is considered ambiguous when the receiving entity cannot tell whether it applies to a previously victimized memory block or to a memory block that the entity is waiting to receive. When an entity receives such an invalidate message, it stores the message in its miss address file (MAF). When the entity subsequently receives the memory block, the entity “replays” the Invalidate message from its MAF by invalidating the block from its cache and issuing an Acknowledgement (Ack) to the entity that triggered issuance of the Invalidate message command.

Abstract: A computer system supports a first set of processors configured to operate in a dirty-shared mode and a second set of processors configured to operate in a non dirty-shared mode. The computer system may include a portion of shared memory that stores data in terms of memory blocks. Upon receiving a snoop read requesting shared access to a memory block held in a dirty state, a dirty-shared processor sends a copy of the memory block to the originator of the snoop read and retains a valid a copy of the block in its cache. Non dirty-shared processors additionally write the block back to main memory in response to snoop reads and may also send a copy to the originator. Until the write back is completed at main memory or another processor is granted write access to the block, the dirty-shared and non dirty-shared processors preferably continue to satisfy sub-sequent snoop reads targeting the memory block.

Abstract: A retry-based mechanism resolves late race conditions in a computer system between a first processor writing modified data back to main memory and a second processor trying to obtain a copy of the modified data. A low occupancy cache coherency protocol tracks ownership and sharing status of memory blocks. When a memory reference operation forwarded from the second processor results in a miss at the first processor's cache, because the requested memory block was written back to memory, the first processor issues a Retry command to the second processor. In response to the Retry command, the second processor issues another memory reference operation. This time, however, the operation explicitly specifies the version of the memory block being written back to main memory. Once the memory block has been written back to main memory, thereby providing main memory with the desired version, a copy is sent to the second processor.

Abstract: A system and method avoids deadlock, such as circular routing deadlock, in a computer system by providing a virtual buffer at main memory. The computer system has an interconnection network that couples a plurality of processors having access to main memory. The interconnection network includes one or more routing agents each having at least one buffer for storing packets that are to be forwarded. When the routing agent's buffer becomes full, thereby preventing it from accepting any additional packets, the routing agent transfers at least one packet into the virtual buffer. By transferring a packet out of the buffer, the routing agent frees up space allowing it to accept a new packet. If the newly accepted packet also results in the buffer becoming full, another packet is transferred into the virtual buffer. This process is repeated until the deadlock condition is resolved. Packets are then retrieved from the virtual buffer.

Abstract: A directory maintains status information over memory blocks in a shared memory computer system. The directory has a plurality of entries each corresponding to a respective block, and is organized into a main region and a write-back region. The main region has an owner field, identifying the current owner of the block. The write-back region has a writer field identifying the last owner to have written the block back to memory. To write a block back to memory, the owner enters its identifier in the writer field and writes the data back to memory without checking nor modifying the owner field. In response to a memory operation, if the contents of the owner field and the writer field match, memory concludes that it is the owner, otherwise memory concludes that the entity identified in the owner field is the owner.

Abstract: A system permits unacknowledged write backs in a computer. The computer has a plurality of processors and a shared memory. The shared memory stores data in terms of memory blocks, and each processor has a cache. Associated with each cache line is a tag containing the address of the block at that line, and its state. A duplicate copy of the tag information (DTAG) for each processor cache is also provided, and each section of the DTAG that corresponds to a given processor is organized into a primary DTAG region and a secondary DTAG region. The secondary DTAG region preferably stores tag information for a dirty version of a block, while the write back of the block is in flight to memory. This frees the primary DTAG region to store tag information for a block other than the dirty block, but using the same cache line.

Abstract: A computer system supports a first set of processors configured to operate in a dirty-shared mode and a second set of processors configured to operate in a non dirty-shared mode. The computer system may include a portion of shared memory that stores data in terms of memory blocks. Upon receiving a snoop read requesting shared access to a memory block held in a dirty state, a dirty-shared processor sends a copy of the memory block to the originator of the snoop read and retains a valid a copy of the block in its cache. Non dirty-shared processors additionally write the block back to main memory in response to snoop reads and may also send a copy to the originator. Until the write back is completed at main memory or another processor is granted write access to the block, the dirty-shared and non dirty-shared processors preferably continue to satisfy subsequent snoop reads targeting the memory block.

Abstract: The invention provides a system and method for resolving ambiguous invalidate messages received by an entity of a computer system. An invalidate message is considered ambiguous when the receiving entity cannot tell whether it applies to a previously victimized memory block or to a memory block that the entity is waiting to receive. When an entity receives such an invalidate message, it stores the message in its miss address file (MAF). When the entity subsequently receives the memory block, the entity “replays” the Invalidate message from its MAF by invalidating the block from its cache and issuing an Acknowledgement (Ack) to the entity that triggered issuance of the Invalidate message command.

Abstract: A retry-based mechanism resolves late race conditions in a computer system between a first processor writing modified data back to main memory and a second processor trying to obtain a copy of the modified data. A low occupancy cache coherency protocol tracks ownership and sharing status of memory blocks. When a memory reference operation forwarded from the second processor results in a miss at the first processor's cache, because the requested memory block was written back to memory, the first processor issues a Retry command to the second processor. In response to the Retry command, the second processor issues another memory reference operation. This time, however, the operation explicitly specifies the version of the memory block being written back to main memory. Once the memory block has been written back to main memory, thereby providing main memory with the desired version, a copy is sent to the second processor.

Abstract: A channel-based mechanism resolves race conditions in a computer system between a first processor writing modified data back to memory and a second processor trying to obtain a copy of the modified data. In addition to a Q0 channel for carrying requests for data, a Q1 channel for carrying probes in response to Q0 requests, and a Q2 channel for carrying responses to Q0 requests, a new channel, the QWB channel, which has a higher priority than Q0 but lower than Q2, is also defined. When a forwarded Read command from the second processor results in a miss at the first processor's cache, because the requested memory block was written back to memory, a Loop command is issued to memory by the first processor on the QWB virtual channel. In response to the Loop command, memory sends the written back version of the memory block to the second processor.

Abstract: An ordering engine is configured to implement a relaxed ordering consistency model for a stream of I/O transactions initiated in a computer system. The ordering engine examines the relaxed ordering attribute of the transactions in the stream to distinguish payload transactions, which may be processed out of order, from control transaction which must be processed in strict order. The engine preferably organizes the stream of transactions into epochs, where the receipt of a first relaxed order write operation in the stream constitutes the start of an epoch and the receipt of a first strict order operation in the stream constitutes the conclusion of the epoch. The engine is configured to delay the completion of the strict order operation constituting the conclusion of the epoch until all payload write operations issued during the epoch have committed.

Abstract: A credit-based, flow control technique utilizes a plurality of counters to conserve resources of a switch fabric within a modular multiprocessor system while ensuring that transaction packets pending in virtual channel queues of the fabric efficiently progress through those resources. The multiprocessor system includes a plurality of nodes interconnected by the switch fabric that extends from a global input port of a node through a hierarchical switch to a global output port of the same or another node. The resources include shared buffers within the global ports and hierarchical switch. Each counter is associated with a virtual channel queue and the flow control technique uses the counters to essentially create the structure of the shared buffers.

Abstract: An initiate flow control mechanism prevents interconnect resources within a switch fabric of a modular multiprocessor system from being dominated with initiate transactions. The multiprocessor system comprises a plurality of nodes interconnected by a switch fabric that extends from a global input port of a node through a hierarchical switch to a global output port of the same or another node. The interconnect resources include shared buffers within the global ports and hierarchical switch. The initiate flow control mechanism manages these shared buffers to reserve bandwidth for complete transactions when extensive global initiate traffic to one or more nodes of the system may create a bottleneck in the switch fabric.